This year’s IEEE Semiconductor Wafer Test Workshop started on Sunday June 10th with a pleasant surprise. Due to a welcomed but unexpected wave of seventy walk-in registrations, there was insufficient seating at the opening dinner. Thankfully the hotel staff quickly adjusted to accommodate these additional guests. Attendance and interest in this year’s workshop was clearly up.
Jerry Broz, general conference chair, welcomed everyone with a brief overview and presented prizes for the first annual golf tournament. We then quickly proceeded with business as Matt Nowak (Senior Director, Advanced Technology, Qualcomm CDMA Technologies) provided the keynote “Emerging High Density 3D Through Silicon Stacking (TSS) – What’s Next?” Mr. Nowak discussed the increased amount of hype within the 3D semiconductor packaging market in the last year with everyone announcing something. And Thru Silicon Vias (TSVs) technology has already been in high volume production for image sensors for several years now but at a significantly lower density than for 3D packaging.
Why the great interest recently in 3D packaging using TSVs today? Three simple reasons: economics, power, and size. The mega economic trend of the electronics industry, 29% per year cost reductions predicted by Moore’s Law, continues to push for new solutions to provide lower costs especially as photolithography becomes more expensive. As mobile devices continue to dominate the market (see Two Conferences – Two Industries Challanged by Post PC Era for my discussion of the “Post PC Era”) issues of power and size are becoming critical. Power is not just the concern over battery life of a mobile device. As mobile devices become more powerful, there is an upper limit on how fast they can operate and how many processor cores can be active at a time. A mobile phone can only dissipate about 3 W of power before the case goes above 40 C and the phone becomes too hot to handle. And for many applications, especially mobile devices which everyone wants to be smaller or which require a larger battery to operate longer, there is a concern over volume not just the planar (“X” & “Y”) size of a device. 3D packaging helps to address all of these challenges.
Qualcomm has moved past PowerPoint slides by building actual 3D parts with up to five die. Today the limit to stacking is economic based upon yield, cost of test, and ability to repair defects once stacked. They have also examined using two die in the older process node (say 32 nm) in a 3D package versus building a single die in the latest process node (28 nm). A good window of opportunity where it makes sense to use the older die in a 3D package is either when this can accelerate time to market (i.e. the newer process node is still very expensive or not yet ready) or where the die is extremely large (hence the yield will be very low in the newer process node for some time).
Over time, the industry has developed a long list of concerns in regards to implementing 3D packaging using TSVs. Mr. Nowak reviewed these concerns and the status of Qualcomm’s analysis of each. The concerns were broken in to the following topics: reliability testing, process concerns, design process for memory die on logic die, product concerns, and TSV technical challenges. In all of these areas, many subitems were proven to not be a challenge. Some of the subitems, especially reliability testing which often takes extended time to complete, are still underway. He highlighted a few areas that still remain problematic:
- Testability – test methods and needed infrastructure are still being developed. They do not yet have a solution for repair after assembly – i.e. how to correct for an assembly process defect or a defect in each die discovered after the stack is assembled.
- Yield & High Volume – Many yield issues, including process sensitivities, only become apparent once products are ramped to high volume. Yes, Xilinx has been shipping their Virtex part using 2.5D packaging for almost a year but their volume is still fairly low. Qualcomm measures volume in billions.
- Design Challenges – There are many new items to be considered when designing a 3D package that may impact product reliability. For example, it is undesirable to have the hot spots (areas that tend to heat up faster) on each die aligned in the stack. It is far better to distribute hot spots when designing each chip such that the adjacent die in the stack actually dissipate the extra heat. In addition, there may be similar localized mechanical stresses on each die that interact once stacked resulting in problems.
Mr. Nowak concluded by saying that the semiconductor “game” is changing; it is no longer about architecture and differentiation will come from packaging. It is really the system software and chipset architecture that drives the product. Over two-thirds of the engineers at Qualcomm are software engineers. And the 3D packaging of stacked chips provides a “new bag of tricks” for chipset architects. There is now momentum in the development of TSV technology and associated infrastructure to make 3D packaging real, however the biggest challenge currenty is the high prices from suppliers.
In terms of product development, we will initially see memory stacking (especially for higher value data center applications and to replace the package-on-package (POP) stacks of memory on microprocessors) followed by 2.5D interposer applications, then logic-on-logic applications, and finally 3D stacks side-by-side on interposers. These will present plenty of challenges in stacking silicon and opportunities to keep everyone busy.
- What are some of the product specific thermal concerns? One needs to consider the product space first since there are very diverse set of products using silicon vias. In his world, a device typically uses a few watts of power. But a large central processing unit (CPU) may have a thermal solution that is very different. A CPU may have air-cooled heat sinks whereas a heat sink or a fan can’t be put in a mobile phone. 3D stacks using wire bonds have been in production for many years where the same thermal concerns as those with TSVs generally apply. With 3D packaging less power is required so thermal management should be better. In terms of the heat path for POP most of the heat goes from the die to the printed circuit board (PCB) to the skin of the phone. In 3D stacking the backside of the die can be made to move the heat in a similar fashion. And the input-output (I/O) buffers are designed for very low drive strength since the adjacent die is so close and there is no need for electrostatic discharge (ESD) structures, etc. that can increase capacitive load requiring additional power to overcome. Therefore, the 3D device can operate at very low energy levels which also reduces the heat produced.
- JEDEC is working to implement more design for test (DFT) for memory devices. This is a major issue for commoditization. How is Qualcomm addressing this issue? Qualcomm didn’t want to create a custom proprietary memory, hence they fully support JEDEC’s efforts. They ship over one billion chips a year using all the foundries and most of the outsourced assembly and test (OSAT) companies. Therefore standard wide I/O memory is critical since they use one suppliers low price to drive the price down across all suppliers.
- What we will see first in terms of devices? A single memory die will be stacked on a single logic die for mobile applications. This memory die won’t need TSVs since it can be attached face-to-face to the logic. Graphical processing units (GPUs), servers, etc. can tolerate more expensive memory so they will have multiple memory dies stacked via TSVs.
- How should several devices assembled (stacked) together be probed? Mr. Nowak is at SWTW to learn from us and he hopes the answer is in this room. Gary Fleeman (Advantest) can talk about Wide I/O memory since he’s been involved with the JEDEC standard. These devices “cheated” by adding a redistribution layer (RDL) to provide standard memory test pads instead of probing the TSVs. The test challenges will be addressed by DFT, test probes, known good die (KGD), etc. Probe cards used to probe the TSVs probably will not be put in to high volume manufacturing (HVM.) But they definitely will be needed during initial device characterization. Fundamentally we need to architect defect resilience into the system so one defect doesn’t kill a whole stack of chips.
- Based upon experience, we are expecting lots more of issues at HVM. What is the timing for HVM for memory on logic (MOL)? What are the unknown unknowns at HVM? Mr. Nowak wouldn’t answer the first part of the question about the schedule for releasing MOL stacked 3D packages since Qualcomm is not saying anything publicly. But he said one could assume the timing is based upon the availability of Wide I/O memory plus qualification time of the new devices and processes from the memory foundry through attachment. 3d packaged devices are coming close to being ready however they have built thousands of parts not millions of parts so there may be more unknowns out there. New issues with all kinds of technology aren’t often found until HVM occurs.