IEEE Semiconductor Wafer Test Workshop 2012 – Welcome & Session 1 (Monday)

Semiconductor wafer test workshop swtw sign 500x352

Here are the highlights from the Welcome and Session One “Process Improvements for HVM” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 11, 2012.

Jerry Broz (SWTW general conference chair) started with several sets of numbers: SWTW attendance (up), semiconductor revenue and wafer statistics (problems). and probe card market (up). The problem with semiconductor statistics are the previously reported discontinuance of the Semiconductor Industry Capacity Statistics (SICAS) and the withdrawal of Intel and AMD from the World Semiconductor Trade Statistics (WSTS). These were both datasets used by the entire semiconductor supply chain – including probe card manufacturers – to provide a barometer for future business.

Lastly, Mr. Broz shared a high level summary of the probe card market in terms of revenue and market share based upon VLSI Research’s annual probe card market report. (For my take on probe card market data please see Probe Cards & Dart Boards and Yes, 40%, Most Likely.)


Keith Breinlinger (FormFactor, Inc.), “Crossover in TD Efficiency – When Brick Wall is Not the Best”:

Awarded Best Tutorial

This was an analysis comparing the number of touchdowns (TDs) required for a  “brick wall” probe head (PH) to a full wafer contractor (FWC). The brick wall PH is where all test sites are adjacent to minimize the active area of the probe array. For example, a 64 site or device under test (DUT) probe card in brick wall configuration might be eight rows of eight test sites or four rows of sixteen test sites sometimes with gaps between the sites (skip row or skip column). Whereas a FWC has the test sites distributed across the full wafer area to minimize the number of touchdowns and the distance the probe card needs to travel. Often these patterns may appear in bands or arches (due to round geometry of a wafer) with empty test sites between the bands forming a “rainbow” pattern.

From analysis of multiple designs and optimization of wafer stepping patterns (sequence of TDs), simplified formulas (rules of thumb) were provided to easily determine the most efficient configuration. In general, when the number of sites on the brick wall probe head is greater than the number of the TDs required, the FWC requires fewer touchdowns. And If the PH contains skip rows or columns or both, the FWC is more efficient at even lower ratios of number of sites to TDs. Improved efficiency was reported in the range of 17 to 33% for the example scenarios.

Additional benefits of FWC typically include: improved electrical performance (less cross talk from distributed test sites and area for analog components), probe force spread across the entire prober wafer chuck, and greater thermal stability (chuck covers most of the probe card). Due to the larger size and complexity, FWC are typically more expensive than brick wall configurations. However, analysis of the return on investment (ROI) often shows that the FWC’s reduced touchdown count translates to substantial savings over the life of the probe card that far exceeds the initial price difference.


  • What is the difference between a rainbow pattern versus distributed DUTs (in a grid) on a FWC? At higher parallelism rainbows become more efficient than a grid pattern. And at lower DUT counts, distributed DUTs are simply a sparse rainbow.
  • What is the planarity specification for a one touchdown or FWC probe card? How about electrical planarity – first to last touch? Planarity is usually around 25 µm. The electrical planarity depends on how stiff your test cell is. Total travel of the probes (first to last) is typically 30-35 µm.
  • The analysis only considered touch down efficiency between probe card types. Are there other factors to consider? Thermal management, etc.? There is no hard and fast rule on other issues such as cross talk. These other factors are very device specific. In general, there is far greater efficiency with a FWC type solution.
  • Did they examine other probe head shapes such as diagonal, diamond, etc? They found with some designs that did not do as well as indicated by the formulas are situations where you need to go look for non-regular shaped solutions.


Doron Avidar (Micron – Israel), “Floating Touchdown ‐ New Methodology for High Parallelism Testing Driving Test Time Reduction”:

A tester needs to wait until all the DUTs finish testing before stepping the prober to the next touchdown. Since a test program may contain conditional branches that are executed based upon the test responses received from a DUT, not all DUTs will take the same time to test. Therefore the time to test an entire wafer is the sum of the slowest DUTs on each touchdown.

Micron built a probe card that contacted all 800 DUT sites on the wafer but are multiplexed to switch between multiple sites. In other words, they have moved from mechanical (moving the probe card to select the DUT to be tested) to electronic switching. The odds that one electrical site has all the slowest dies is very small. In this example with six die per electrical site, it is approximately one in twenty six million. By moving to electronic multiplexing instead of six physical touchdowns, the test time was reduced by 23% per wafer.

The biggest challenge of this approach is the complexity of the probe card due to additional switching components which also impact the signal integrity. The test program is also more complex since it has to control the different electronic switches and to operate each test site independently of the other test sites. However, with possible savings on the order of 25% they will definitely evaluate this option for future products.


  • With regular touchdowns, do you do test all the die for continuity first and then skip the longer test for dies that fail? You could do that to decrease test time.
  • What is the required probe force to touch all die with probes at the same time? This is an important aspect but they didn’t extensively investigate issues of the FWC for this study. Force on chuck, planarity, etc. are important but a different aspect of this type of solution.
  • What if the parallelism was 144 DUTs versus full wafer? What if you could touch half the wafer at once? This is really a new concept for Micron so they haven’t looked at this scenario.
  • What is the break even point based upon the variability in test time? Different wafers of the same design will behave differently. Some have 5%, others 25% test time reduction. They are still figuring out how to calculate or optimize the method.
  • What is the mechanical or electrical life of switch matrix? Micron is still looking for the best electrical switch. and don’t yet have an answer.

Luc Van Cauwenberghe (ON Semiconductor – Belgium), “Wafer Probe Challenges for the Automotive Market”:

Co-Award for Best Data

Automotive customer test requirements include testing across the full range of specifications (typically -55 C to 200 C). ON Semiconductor characterized the movement of probes based upon thermal issues. They found at cold temperatures the probe card moves less than when hot. As expected, large movements in the probe card as it heats up or cools is a function of the location of the wafer chuck (containing the heat source). When the wafer chuck remained close to the probe card, the temperature of the probe card showed the smallest fluctuation resulting in the smallest probe movement. The further the chuck moves from the card the greater the change in temperature resulting in greater probe movement.

As part of this project, a “bridge stiffener” was designed and patented to reduce the movement in Z height of the probe card regardless of the coefficient of thermal expansion (CTE) of the different printed circuit board (PCB) material that might be selected. The CTE of the PCB material is often the dominant factor in movement of the probe card.

They also changed from cantilever to vertical (buckling beam) technology probe cards to reduce the movement in the X / Y plane due to thermal effects. Their customers typically require probe marks to be less than 28 µm in diameter (615 µm2 disturbed area) regardless of number of test insertions – i.e. times the individual part is probed. The vertical technology also reduces the area of the disturbed pad and depth of the scrub marks. With cantilever type probes, multiple touch downs tend to lead to large scrub mark areas above the customer limit. Due to the higher positional repeatability of the vertical probes, there needs to be care to not exceed the probe depth specification with multiple touchdowns.

ON Semiconductor nows has test solutions working at 175 C. They are attempting to expand testing to 200 C and to increase the number of multisite setups. They also plan to study the impact of temperature on contact resistance (Cres).


  • For cold testing are they using an enclosed prober or a cold chuck? They are using a standard Accretech UF3000 prober with a cold chuck.
  • Are they seeing any differences between probe cards with single or multiple sites? Thermal soak time is necessary to bring the entire card to the right temperature. The size of probe card may have an impact on the time required. They currently only test 16 sites in parallel so most cards are roughly the same size requiring the same soak time. They only perform the soak at the start of the wafer lot.
  • How do they measure the Z deflection of the probe card? They measure it with the build in prober vision system and they double check with a displacement sensor on top of the probe card. 
  • At 200 C can they use FR4 for their PCBs? They have switched to FR5 with a higher temperature rating. 
  • When the temperature drifts, is the scrub location changing due to the change in Z position? Yes, even vertical probe cards change scrub with the movement in Z.
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