Here are the highlights from Session Six – “Probe Potpourri” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 14, 2011.
Marc Knox, IBM, “The Development of a Flexible and Efficient Chip Thermal Imaging Capability“:
Traditional burn-in systems hold multiple printed circuit boards (PCBs) with one or more devices in burn-in sockets to provide temporary electrical interconnect to a device under test (DUT). These PCBs and sockets are known as “burn-in boards”. And the systems in which they are loaded are “ovens” that permit temperature stressing, sometimes at both hot and cold temperatures, while stimuli are supplied to the chip. The purpose of “burning-in” a device is to screen for infant mortality in an accelerated manner.
The IBM team adapted a burn-in board system to permit the thermal imaging of an integrated circuit (IC) during operation. Instead of an oven with multiple burn-in board slots the thermal imaging system was based on a diagnostic system with a single slot. Even with one burn-in board slot, the system has all the control and functionality of a full oven including a thermal fluid cooler system to manage chip temperatures.
Many devices for IBM use the C4 flip chip assembly process to attach the IC to a package substrate. The package substrate is then soldered to the PCB board in the final device being built. In this flip chip configuration the transistors face the substrate and only the “back side” of the silicon (i.e. the wafer on which the transistors are built) can be exposed when the device package is opened. In order to increase the thermal contrast the silicon can be thinned by back grinding to provide a better analysis of the thermal gradients across the integrated circuit.
In order to regulate the DUT temperature the cooling fluid is pumped across the die below a glass window. The glass window contains the cooling fluid while allowing the thermal imaging to be performed. System software controls both the stimulation of the DUT and the thermal imaging.
This system has become very handy in investigating thermal issues with devices both under development and in production. A case study of the C4 “pullout” problem for the Power7 processor was presented. The “pullout” failure mode is where some of the C4 solder bumps on a wafer become detached after wafer probing. With the missing solder bumps the dies have to be scrapped since the C4 flip chip attach cannot be completed due to electrical opens from the missing bumps. The thermal imaging enabled quick identification of the root cause which in this case was a wafer processing sensitivity and not a probe equipment issue. The quick resolution of this problem, allowed the Power7 to quickly ramp in to high volume production.
- Who manufactures the FC-77 cooling liquid? He believes that Dow Corning provides the fluid.
- Is there a gap between device and glass? Yes, there is a gap for the fluid flow.
- Does the thermal test systems have the same connections as with package part tests and can it run the same tests? In this particular case no and it didn’t matter. The “pullout” problem was a leakage phenomenon (not test pattern related). But when needed there is the capability to run package tests. And there is remote access so chip designers can remotely look at the infrared (IR) images, etc. from their desks without going to the test floor.
Mike Fredd, Cascade Microtech, “The Electromechanical Design of Spring Pin Based WLCSP Contact Engine and Its Effect on Signal Fidelity“:
A “Contact Engine” is both the spring pin and the dielectric housing used to contact wafer level chip scale packages (WLCSPs). Typically these are used to probe die with solder bump pitches of 300 to 500 µm.
There are many challenges when modeling Contact Engines to determine the electrical performance of a specific design. The simulation needs to model both the spring pin and the dielectric housing since both the dielectric itself and the configuration of the pins is critical at higher frequencies. And lumped element models are only valid when signal length is less than 1/10th of the wavelength. If this is not the case, microwave modeling needs to be used.
For optimal power and ground distribution, partial inductance should be calculated based upon mechanical parameters. Care needs to be used since inductance values in spring pin data sheets are not consistently determined between vendors. On the other hand, to address high bandwidth requirements controlled impedance is required not the lowest self inductance. In this case the dielectric selection and configuration is critical to reduce the impedance mismatch.
The best approach is a three step process:
1. Use analytical techniques to define the scope of the problem.
2. Perform simulations to provide greater details.
3. Confirm via measurement on actual hardware.
- Is the data shown a real configuration? Yes, it is with a 50 ohm load.
Behrouz Sadrabadi, Qualmax America, “Novel Vertical MEMS Probe Card for High Speed Devices“:
A new vertical micro-electromechanical system (MEMS) based probe card has been developed. This product is the result of a partnership of GigaLane, who performs the manufacturing, and Qualmax. Qualmax works with the customers to provide sales, marketing, qualification testing, and application support.
The architecture is based upon a 500 µm thick silicon (Si) wafer that is deep reactive-ion etched (DRIE) for the guide plate. Similar to other vertical technologies, the guide plate positions the vertical probes. Since the plate is silicon it is thermally matched to a silicon wafer since the thermal co-efficient of expansions (TCE) are very close.
Currently the probes are available in two styles: buckling-beam and spring style. The probes are electroformed followed by a chemical-mechanical planarization (CMP) step. Nominal thickness is 20 µm and there are approximately 20,000 probes on an 8″ wafer.
The space transformers are also built on a silicon wafer (similar to a flex circuit) which are in turn wire bonded the PCB. Double sided space transformers are under development to eliminate the need for wire bonding.
Three example designs were shown: a Wide I/O memory device with bumps on 50 µm x 120 µm grid, a 50 µm fine-pitch configuration for testing sixteen system-on-a-chip (SOC) devices in parallel, and a large area (60.7 mm x 121.4 mm) design with 9,600 probes.
- The Wide I/O device shown has a 50 µm x 120 µm pitch. How is a 50 µm x 40 µm pitch which is the actual Wide I/O specification achieved? The design shown skips device pads per the customer request. For this application the “magic” is in the DRAM device side. In any case, a 50 µm x 40 µm pitch can be achieved.
- What cleaning media is used? A cleaning protocol hasn’t been developed yet.
- What is the tip material? It is the same as the body of the probe which is nickel-cobalt (NiCo). However, this can be modified if needed.