IEEE Semiconductor Wafer Test Workshop – High Temp / Extreme Probing – Session Seven (Tuesday)

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Here are the highlights from Session Seven – “High Temp / Extreme Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 14, 2011.

Kevin Fredriksen, SPA GmbH, MSO – Multi-Site Optimizer”:

Most wafer probers do not supply intelligent stepping algorithms to calculate the most efficient sequence of moving the wafer relative to the probe card. (Ed: At the core of this is a traveling salesman problem.) The situation is exacerbated when multi-site probe cards are used since the spatial configuration of the probe card needs to be taken into consideration. The Multi-Site Optimizer (MSO) software will calculate the most efficient positioning of a multi-site probe head and the shortest path of travel. The resulting stepping patterns can than be used to program the prober. The MSO software can also calculate the most efficient probe head configuration for a given number of sites to be tested in parallel.

MSO can also calculate stepping patterns where each site of the multi-site probe only contacts a die to be tested (“inclusive” testing) and not the process margin of the wafer. An example application for a micro-electro-mechanical system (MEMS) sensor wafer was shown with the unique challenge that every other die was rotated 180 degrees. By building a special four site probe card with two of the sites rotated, it was possible for MSO to calculate an inclusive step pattern for this device.

Lastly, MSO can calculate special stepping patterns including those that increase the thermal soak time of dies on the wafer’s edge.


  • Is this commercially available software? Yes, it is commercially available.
  • How long does it take to run? Touch down positioning takes 2 to 3 seconds. A stepping path for 2 mm square dies takes approximately 8 seconds. Perhaps up to 1 minute for very small die.
  • When you optimize stepping patterns can you set the maximum number of touches for a given die? Not a current feature but it could be added to the software.
  • Can offsets be staggered between left and right sides? Currently the software optimizes from top to bottom and left to right. This could be done as a customization.
  • How long does it take to set up the wafer map on the prober? They are currently importing an Accretech prober map through a converter and it writes out a file for the prober to use.
  • Does it help to optimize the stepping pattern for retest? Not a current feature but it could be added.


Jan Martens, NXP Semiconductors, “Identification, Analysis and Control of High Temperature Influences on Wafer Test Probing Processes”:

High temperature probing at temperatures as high as 200 C provides substantial challenges especially as pad sizes shrink. Three design of experiments (DOE) were constructed to test both the probe to pad alignment (PTPA) algorithms of the probers and to evaluate process analysis tools.

Both thermal stress factors (those directly related to the thermal heat applied) and mechanical stress factors (accuracy in mechanical design) were identified. There have been many good papers presented at SWTW about improving the engineering of probe cards but the team wanted to focus on process solutions that could be implemented with their existing probe cards.

The experiments and results were:

  1. Comparison of in house solution to Rudolph Technologies’ WaferWoRx process analysis tool by measuring intentional errors on ten wafers. Both systems showed equal capability.
  2. To determine the best stepping pattern for high temperature probing at 125 C. MSO software (described in the prior presentation) was used to generate stepping patterns. WaferWoRx analysis plots were informative but did not provide quantitative data to compare these stepping patterns and determine the best pattern. Additional analysis with Microsoft Excel was required. As a result NXP made some suggested improvements for WaferWoRx including time series, video 2D plots, etc.
  3. To establish which realignment settings for PTPA should be used for high temperature. Using a video plot they could watch alignment shifts over time to determine the proper realignment interval. With realignment they have effectively shrunk the scrub mark window by almost half.

Temperature difference from ambient has the most significance in terms of alignment error.


  • On the third DOE the plot “Comparison X Position” why is there a significant difference between the 200 C and 175 C data? These tests started at different X locations.
  • How should the cooling of probe head during a probe cleaning execution be handled? You can set a time limit on the cleaning and if the cleaning takes too long you should perform a re-alignment (PTPA).
  • Was probe mark data from the Rudolph tool used? Could prober probe mark inspection data be used? Yes their analysis could have done with the raw data from either tool.
  • Was the temperature soak of the probe card done in or out of contact with the wafer? It was done out of contact but they didn’t get permission to disclose the distance setting.

Audience Comment: A spiral stepping pattern had been used in the early DRAM days driven by yield. The user started probing at the middle of the wafer where there are typically fewer Cres issues. And if you encountered losses due to Cres (typically probes getting dirty) as you reached the edge it was less of an issue since there was lower die yields towards the edge.


E. Boyd Daniels, Texas Instruments, “Ultra High Temperature Probing”:

The need to test at high temperature (200 C) is driven by two product groups at Texas Instruments (TI): High Reliability and Automotive Applications. The High Reliability group desire is for parts to operate reliably under extreme conditions. While the Automotive Applications group needs parts with zero defects at the parts per million (0 dppm) level. In order to meet the needs of both groups, they had to revisit the entire probe process to evaluate their capability and make the required adjustments.

A thermal wafer with embedded resistive thermal devices (RTD) and thermocouples placed within the prober and on the probe card was used to characterize the probe environment. Some initial findings included:

  • After 55 minutes of heating the prober from room temperature to a setting of 200 C, the prober reported “ready” while the wafer was only at 185 C. It took an additional 17 minutes for the wafer to actually measure 200 C. Therefore, a longer setup time than the prober reports is required to achieve the desired temperature.
  • A 4.4 C delta in temperature across wafer was observed due to the airflow from the fans in the prober chamber. They decided to turn these cooling fans off while performing high temperature probing to reduce this variation.

Due to the very low volume of wafers requiring 200 C testing their standard qualification process was altered to gather enough probe card usage to validate their revised process. In order to increase the number of touchdowns a blank aluminum wafer (300 mm / 20K touchdowns per wafer) was probed between every product wafer (200 mm / 754 touchdowns per wafer). This increased the total touchdowns to over 103 K during qualification testing.

In terms of test results, the commodity product wafers had previously been tested at 30 C and after testing only the known good dies (KGD) at 200 C there was a yield loss of approximately 50%. In the data shown for the contact resistance (Cres), one can see a substantial reduction can be seen in the range of variation when switching from a dual site cantilever card to a x16 MEMs probe card at 30 C. The vertical buckling beam probe card from Feinmetall being evaluated at 200 C also showed very stable Cres measurements with a standard deviation of 0.4 ohms or less. However, there was a significant increase in the value of the Cres due to the change in diode values at the elevated temperature.

The next area to investigate is can the process be repeated up to 220C? And with only one supplier for 200 C, a second source to qualify is desired.


  • What was the type of probe card used and how do they clean it? It was a vertical type probe card. They used a Feinmetall proprietary cleaning material, which is a polymer with abrasive, designed for high temperature usage.
  • Does the polymer melt at high temperature? That is why they have a proprietary material.
  • Is the TI methodology to measure contact resistance of every failed die? Yes a measurement through the diodes is taken for every die. They don’t exclude the diode value from the measurement. Therefore their “Cres” values shown are really the path resistance from test head through the probe card to the wafer.


Gunther Böhm, Feinmetall, “Contact Formation in Wafer Test Probing – Fritting, Breakdown, Pad Damage and Conduction”:

Current methods of probing are rather aggressive with typical scrub marks of 200 to 800 nm. This becomes an issue as pads over active area (POAA) become more common. The old rule of pressing harder to make better contact needs to be revisited.

A series of experiments were constructed to examine probes on different materials and to look for fritting. Fritting is the effect of non-conductive films between metal contact surfaces. (Ed: Jan Marten describes fritting in his excellent 2006 SWTW paper and Paul G. Slade discusses it “Electrical Contacts: Principles and Applications”)

A ViProbe S-Type 59 um pitch probe card was used as a test vehicle with 45 probes. (The same type of probe card used by Boyd Daniels in his work presented prior to this presentation.)  Since things going well are not very exciting, they set up some worse case conditions to look for failure including no cleaning, reducing over travel (hence force) for some touchdowns, and changing pad metals going from copper to aluminum to gold. The tests were performed both at nominal 28 C and 180 C.

In terms of metallurgy the team concluded:

  • Aluminum probing is very stable even under bad conditions.
  • Copper has a wide variation in types (specific metallurgy, surface roughness, etc.) and can have a wide variation of contact quality across the same type. Copper is sensitive to the cleanliness of the probe tips and cleaning recipes need to be developed for each type of copper.
  • When tips are contaminated with copper and aluminum oxides even contact on gold fails. Therefore consistent gold probing requires fresh tips.

With regards to fritting they determined it requires a minimum current and voltage to occur. And the fritting does not “heal” the contact to provide stable contact resistance.

To study films and other contaminates on pads, scanning tunneling spectroscopy was used for non-contact measurements to show the difference between the metal types. To further optimize the scrub damage scrubs marks and tips were measured with atomic force microscopy (AFM). These AFM measurements are being correlated to results from finite element analysis (FEA) predictions of the scrub mark. The reason to use FEA simulation is that it is far faster than doing actual experiments. However, additional work is needed to improve their simulation capability to get closer to actual results.


  • Why not try to clean the probes to see what happens? Cleaning experiments were done but it was too much data to present.

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