IEEE Semiconductor Wafer Test Workshop 2012 – Session 4 (Monday)

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Here are the highlights from Session Four “New Contactor Technologies and RF PCB Design” of the 22nd annual IEEE 
Semiconductor Wafer Test Workshop (SWTW) from Monday June 11, 2012.

A last minute change to balance the schedule moved my paperThe Road to 450 mm Semiconductor Wafers” from the previous session:

Many believe that Gordon Moore in his famous 1965 paper “The Experts Look Ahead: Cramming More Components onto Integrated Circuits” that has become know as Moore’s Law, said that the number of transistors on a device would double every year (later revised to every two years). He did not say quite that. What he said was the minimum cost per transistor was obtained by doubling the number of transistors on a device every two years. Moore’s paper was an economic marketing promise, not a technology projection. As such, the electronics industry has attempted to keep on this cost reduction curve.

In the past, photolithographic scaling was used to reduce the size of the transistors by as much as half. However, now as both photolithography and process complexity have significantly increased there is a concern that these shrinks alone will not keep the industry on the required trajectory. Cost concerns coupled with the demand for increasing quantities of silicon has turned industry attention to the next wafer size. By increasing the diameter of the wafer by 50% from 300 to 450 mm, the area will increase by 2.25x. And if the incremental cost for processing the larger wafer can be held to 12.5%, which may be achievable, the cost per area for the 450 mm wafer will be half that of the 300 mm. Therefore increasing the wafer size would be equivalent to one node on the price curve.

There are many technical challenges from the size and weight of the required wafer probers, to work in process (WIP) cycle time impact, to supply chain issues for obtaining printed circuit boards (PCBs) and other materials. And there are many mechanical challenges including the force exerted by upwards of 315 K probes and the shift in probe position due to thermal movement of the probe card.

At the same time, there will be economic challenges to carefully manage both the cost of the transition and the incremental cost for the larger wafer size. In the wafer fabrication process flow, there are only four processes that are serial in nature requiring additional time due to the large wafer area: photolithography reticle stepping, ion implantation, metrology and inspection, and non-full wafer test. There will be great pressure on all of these areas to simultaneously increase the throughput and reduce the cost per die or area. For the transition to 300 mm wafers, Intel set strict limits on the relative capital cost and relative footprint on all new tools to achieve their production targets without increasing the size of their factories.

The “elephant in the room” is how the semiconductor equipment manufacturers will recover their investment to develop the new equipment required to move to 450 mm. At this year’s SEMI Industry Strategy Symposium (ISS) (my summary post is here), Mike Splinter chairman and CEO of Applied Materials pointed out that the 300 mm wafer equipment had a total industry investment of $12 B which took fourteen years to recover. The current estimate is $15 to 20 B for the development of 450 mm equipment with an unknown time to recover. Obviously a topic of much “discussion” and “negotiation” between equipment suppliers and semiconductor fab operators – integrated device manufacturers (IDMs) and foundries alike.

Possible solutions for testing 450 mm depend on where the testing is to be performed and in what timeframe. For in-process parametric testing the wafer cannot be modified which greatly reduces possible solutions. For the research & development (R&D) phase the use of manual or semi-automatic probe stations is likely. For initial short term production, it may be possible to use a flying probe system to delay investment in new equipment. In the long term, a super-sized version of existing probes is the most likely solution.

After the wafer has completed “front end” processing, more options exist since the wafer can be modified. During the R&D phase, a simple solution may be to cut the wafer into four quarters. Each quarter is close or smaller than a 300 mm wafer in overall dimension. Yes, this may be an “inefficient” solution both in terms of throughput and possible loss of a few die (due to the die layout) but it will allow the use of existing equipment with very little operational changes. In the short term, if it is desired to not invest heavily in new equipment, reconstituted wafers can be used where singulated die are reassembled on a carrier in efficient to probe shapes.

For the long term, where die are tested in low parallelism (from one die at a time to dozens at once) the likely options are a super-sized wafer prober or handling singulated die with a process such as Centipede Systems’ Test-in-Tray. For those parts tested in very high parallelism (often with full wafer contactors that cover the area of the entire wafer and enable one to four touchdowns per wafer), simplified probers with a restricted range of motion may be the appropriate solution. There are also several companies working on new test cells concepts to further increase efficiency and reduce the cost of test. I trust that these new concepts will scale to 450 mm.

In summary, there are challenges that are 1.5x current challenges while others are 2.25x with the transition to 450 mm wafers. The good news is there are multiple solutions to the technical challenges but they require planning to be ready at the right time. The largest challenge is financial as every solution will need an adequate return on investment (ROI). Companies, semiconductor and equipment manufacturers alike, do not want to over invest or miss the opportunity. At the same time, disruptive change may occur since inflection points are often the best time to introduce innovative solutions.


  • Which type of devices are likely to transition to 450 mm wafers first? The parts that will see the greatest benefit from 450 mm wafers will be those that run in extremely high volume such as microprocessors and memory devices. From press accounts, it sounds as though Samsung has said that they will let Intel lead the way and go first. If true, I assume that we will see microprocessors on 450 mm first.


Jon Diller (Interconnect Devices, Inc.), “Are Spring Probes Valid Below 400 Micron Pitch?”:

When compared to spring pins, cantilever and vertical probe solutions have limited array depth, reduced mechanical compliance, difficult repair, and high cost of use. The comparative advantages of floating spring pins are high reliability, excellent radio-frequency (RF) performance, and easy maintenance. A technician can service a spring pin contractor at a rate of one spring pin per minute in the field with only hand tools. Spring pins are however limited to 400 µm or larger pitch. Due to the machining and plating process, it is difficult to manufacture spring pins for use below 400 µm pitch.

To enable tighter pitches, IDI has developed the “Monet” product line as a barrel-less spring contractor. Using an electroforming process, a conductive barrel is permanently formed in the dielectric housing which normally is machined to have the barrel of a spring probe inserted into it. The rest of the spring probe – the two end plungers and coil spring – are then inserted in to this “conductive cavity”.

Using this approach, the spring pin can be made more robust as the diameter of the spring and plungers are increased since there is no longer the gap and associated tolerances between the barrel and the dielectric necessary for the press fit. This great strength also allows the overall probe length to be decreased. Unlike other barrel-less probes, where the current flow is via the spring and there is higher resistance, these conduct through the plated in place barrel with comparable resistance to a conventional spring probe.

Current capacity measurements of the Monet suggests it has 5x the capacity of a comparable spring pin due to the high stability of contact resistance. Having completed lab testing to 500 K touchdowns, IDI is now waiting on field data to indicate on how long the conductive cavities last under production conditions.There are beta sites running the Monet at both 200 and 300 µm pitch.

Though spring contact probes are the preferred solution at 0.4 mm and above pitches for WLCSP, the Monet process will support testing down to 150 µm pitch. Additional developments are underway to further decrease the bulk resistance by increasing the barrel plating and develop a Kelvin measurement solution.

(No questions were asked.)


Zaven Tashjian (Circuit Spectrum, Inc.), “Quantifying the Impact of the Environment on PCB Transmission Lines”:

The printed circuit board (PCB) is the common link between automated test equipment (ATE) and the device under test for both wafer and final (package) test. When designing the PCB, contradictory goals of power delivery with high integrity and bi-directional signal integrity need to be balanced.

Common design issues that may become exacerbated as the signal frequency increases were reviewed in both the time and frequency domains using electrical simulation. These issues included covered and embedded microstrip transmission lines, voids in reference voltage planes, trace width “neck down”, floating metal structures, and parallel conductor crosstalk.

Numerous issues such as these need to be considered during the design process. It is helpful to separate them to appropriate sized structures to enable proper simulation of the design parts. It is currently impractical to simulate all aspects of the entire PCB at one time. However, it is both possible with effort and highly desirable to model critical signal paths from end to end to ensure the design will satisfy the test requirements prior to fabrication of the PCB.


  • With the structure shown on slide 15 why is there an irregular space between the conductors? Mr. Tashjian was unsure since he did not have the data readily available.
  • What is the amount of maximum crosstalk between signals to be permitted? By testing trace to trace distances (which are multiples of the conductor width) it is possible to look at the simulation results in the time domain to make sure no voltage above the noise limit occurs on the victim trace. The end application will dictate what the maximum acceptable level of noise is.
  • What is the definition of embedded microstrip line? This is two dielectric materials directly above and below a trace effectively surrounding it. This structure is more uniform than a microstrip on the outside of the board, but the drawback is that it needs a via to connect to a tester or DUT pad.
  • Typically one will see an Increase in impedance as a trace enters a via field since it is gaining capacitance. This was not see this in the trace neck down simulation presented, was it included? For simplification that was not included in that simulation.
  • What is a stray floating conductor? It is an isolated metal trace or structure that is electrically coupled to a nearby conductor such as a ground plane. The stray metal is distorting the electric field which is compromises the coupling of other signals to the reference plane.
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