IEEE Semiconductor Wafer Test Workshop – Signal Integrity – Session Five (Tuesday)

Here are the highlights from Session Five – Signal Integrity of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 8th.

Gert Hohenwarter, GateWave Northern, Inc., “Hidden Performance Limiters in the Signal Path”:

For high frequency signals, designers typically pay attention to avoiding coupling to adjacent signal lines to prevent cross talk.  However, they need to look at many other areas of the design including coupling to power or sense lines, signal impedance mismatch, resonances, and the power distribution/delivery system (PDS).  Coupling and mismatch may lead to resonances which reduce the operating speed or reduce the switching margin. These areas may also increase crosstalk increasing noise levels and also reducing switching margin. In addition, problems in the PDS may also reduce operating speed or switching margin.

He showed a cross talk example where there were failures of a part at periodic frequencies (as shown in the shmoo plot) due to a bad ground connection in the test setup.  Once the ground connection was improved, a significant percentage of parts that were graded as failing now pass the test.

Other example of problem areas discussed included: guard traces for shielding can actually increase resonance, capacitive loading from tester resource sharing can result in delayed rise time and timing shifts, and coupling to an adjacent open/short pin can change the timing.  In the coupling to adjacent open/short pin example as the distance between the signal pin of interest to the nearest ground increases the coupling effects of a shorted or open pin become worse.  An additional simulation also showed how reducing the number of adjacent grounds worsened the situation.

It is obvious that these types of issue are problematic when testing at high frequencies.  What is not obvious is that these also may show up at burn in test too as device speeds increase and both burn in testing speed increases (to match the device speed) and the devices themselves have faster response times.

His advice is that it is easier to perform design verification early, including signal integrity checks which can be modeled and verified through measurements, than trying to resolve these issues once the test hardware is built and the parts are on the test floor.  Seeming small individual effects can compound and some problems may not be apparent during design but show up in production testing.

Jeff Arasmith, Cascade Microtech, “The Affects of Probe Impedance on RF KGD Measurements”:

Wafer level chip scale packaging (WLCSP) became the most popular package in 2009 according to Jan-Marc Yannou (Yole Research) “WLCSP quietly edges into #1 position” as reported in 3D Packaging  (p. 16) therefore there is a real need to do known good die (KGD) testing today.  To really have KGDs as the parts become faster it is necessary to perform high frequency (i.e. radio-frequency or RF) measurements today.

Probe cards and probe structures typically specify both the bandwidth and contact resistance (Cres).  However, at typical consumer application frequencies the inductance of the probe also needs to be considered.  For example both WLAN and Bluetooth operate at close to 2.5 GHz. At these frequencies, a small inductance of 0.1 nH translates in to 1.6 Ohms and a larger inductance of 1 nH translates to 16 Ohms.  These effects of the inductance are very large relative to the Cres (typically 0.5 to 2 ohms) and for 1 nH it is almost 1/3 of the impedance of a 50 ohm line.

He compared electrical models of their membrane Pyramid Probe to a spring pin and to a MEMS vertical probe mounted on a similar base structure:





Probe Inductance
Probe TypeSignal to SignalSignal to Ground
Pyramid Proben/a0.04 nH
Spring Pin0.68 nH0.68 nH
MEMS Vertical Probe1.05 nH1.05 nH

Neither the spring pin nor MEMS vertical probe have a ground plane underneath like their Pyramid Probe that is why the model includes signal to signal inductance for the spring pin and MEMS vertical probes but not the Pyramid Probe.

They ran HFSS simulations of the MEMS vertical probe and the Pyramid Probe models.  The increased inductance of the MEMS vertical probe resulted in greater cross talk with the model predicting a 10 dB difference at 3.35 GHz.  At -40 dB this would put 10 mV of noise on the victim signal for every 1 V on the aggressor signal.

Therefore, reasonable specifications for probe bandwidth and Cres is not sufficient to test parts at the application frequencies seen today. It is also necessary to understand the inductance & reactance.

Zaven Tashjian, Circuit Spectrum, Inc., “The Importance of the Signal Return Path in Test Applications”:

Increasing data rates in excess of 10 Gbits per second (Gbs) requires greater attention to signal integrity during the design and fabrication of the printed circuit board (PCB). Simplified modeling and simulation may produce inaccurate results at these frequencies. One particular problem area is that ground planes are not really zero impedance as typically is assumed. Therefore, 3D full-wave electromagnetic simulation is required as demonstrated to properly evaluate the signal return path.

He showed how the reflection or return loss (S11) of a signal is a function of frequency and signal return quality by changing the number of and distance between the ground vias and the signal via of interest. In this particular model, four ground vias surrounding the signal via performed better than two ground vias and the closer the ground vias to the signal vial the better. Insertion loss (S21) is also a function of frequency and signal return path quality.  For insertion loss, the two vias case performs about the same as the four vias case however as the frequency increases the distance becomes ground vias and signal via becomes more critical.

Using another example on the ground termination of a sub-miniature co-axial connector (SMA launch), Zaven showed how two constructions have the same 2D model results while the 3D models returns a substantially different answer. Direct measurements showed good correlation to and demonstrated the correctness of the 3D model. By improving this simple termination detail on the connector’s return path they were able to stretch the design from 3 Gbsp to 10 Gbps.

Larry Levy, FormFactor, “Expanding Test Coverage at Sort to Reduce Overall Product Costs”:

This presentation was written by Dale Anderson at National Semiconductor who was supposed to present it, so it is purely their study and data. This was a case study to compare FormFactor MEMS probe cards to cantilever probe cards for two different product types. One device was a high speed (1.6 Gbps) analog digital converter (ADC) and the other was a high power (1.5 A) management device.

One of the unique items in this project is FormFactor’s new “TrueScale Light” format where they provide just the probe head, interposer, and mechanical mounting hardware as complete assembly. The end customer designs and builds the PCB on to which the probe head assembly simply mounts to.  This permits the end customer to focus on the PCB design while FormFactor simply focuses on the probe head design.  Larry also described that it is “hard for FormFactor to do a Teradyne Ultra Flex board” and this circumvents this issue.

Some of the key advantages of the FormFactor MEMS card over traditional cantilever cards identified included:

  • Ability to put components directly on the space transformer resulting in higher signal fidelity.
  • Increased current carrying capacity.
  • Greater ability to correlate between sort and package test.  They couldn’t run some of the package tests at wafer sort using the cantilever probe cards.
  • Approximately 6% higher yield on the ADC part.  Devices that previously failed some of the AC tests now pass and are good.
  • Ability to place Kelvin pins.  On the power management device they placed 2 force pins and 1 sense pin all on one 180 µm x 68 µm pad.
  • Longer life.

However, these came with a longer lead time (due to ceramic space transformer) and initial higher cost.

He showed scrub mark data, contact resistance data, and probe tip wear for the first 375K touch downs. These demonstrated consistent contact resistance (Cres) and low probe wear.

Larry shared National’s Cost of Ownership (COO) analysis comparing the two types of cards. Cost data for card acquisition and maintenance was included on the slides shown.  On the power management device, after only 10 wafers (300,000 total parts) the FormFactor cards saved $169,948 mainly due to 5% better yield at final (package) test since the unit cost (with package) is $236 each.  On the ADC part the savings from using the FormFactor cards was $132,490 over 1,200 wafers.

Next steps are to run the cards to 1M touch downs or end of life with additional studies of cleaning and Cres followed by release to high volume manufacturing (HVM).

Note: I will post the link for the slides once they become available.

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