Silicon Valley Test Conference – Something New & Overdue

Starting off something new is often challenging and difficult with many unknowns. Kudos to Nick Langston for creating the Silicon Valley Test Conference that was held last week. (November 8 & 9, 2010) It was the first test conference to actually take place in Silicon Valley. And yes there were some minor “bugs” like registration delays and a no-show by the audio visual contractor that should be solved in next year’s Rev 2.0. Even with a few rough edges, the quality of the presentations and the exhibitors shined through to make this a success.

The conference opened with an excellent keynote address by well-known industry expert Jim Healy “Speculations on ATE”. Mr. Healy examined both past predictions about the industry and made his own in regards to Built in Self Test (BIST) obsolescing automated test equipment: “When the TeslaGoogle is mainstream the TesterGoogle will be a reality”.

There were two parallel session tracks for the conference, Interface Hardware and Test Methods. Each had seven presentations the first day including my own “Wafer Probe Technology & Application Overview“.

The 146 attendees got their first look at the exhibits when the conference served lunch in the exhibit hall. There were 31 exhibitors all focused on semiconductor test and eager to great old friends and new customers. As I commented to a friend in the wafer probe industry who was thinking about exhibiting next year, though the quantity of leads at a conference this size is low the quality was high due to the focus. And since the cost to exhibit was extremely reasonable, this would likely result in a fairly high return on investment (ROI). Let’s hope that the exhibitors all agree so that they will sponsor next year’s event.

The program on the first day concluded with a panel discussion “ATE Market Drivers for the Next Decade” moderated by Ron Leckie. Mr. Leckie started with an overview of the economic trends of the industry and how Sheth, et al’s Rule of Three may play out in his “ATE Countdown“. He is predicting that there will be consolidation to only three major ATE companies along with a similar consolidation of handler and prober companies.

The panelists, Steve Tilden (Director of Marketing & Technologies of LTX-Credence), Mark Roos (CEO of Roos Instruments), Ching-Too Chen (Chroma ATE), and Marc Loranger (Director of Test Technology of FormFactor) each gave a short overview of the industry drivers they see. Key items of concern expressed:

• Lack of clear roadmaps with ever increasing device requirements and increasing customer base (proliferation of fabless companies) leading to excessively broad requirements. (Tilden)
• Increased need for differentiation including improved software to make ATE systems easier to use. (Tilden)
• The overall mobile phone (handset) market will no longer be a growth engine for ATE since it’s growth has leveled off now that saturation has been reach (53% of the world’s population has a mobile phone which is equivalent to 85% market penetration after removing young children). (Roos)
• Infrastructure (cell sites, pico-/femto-cells, etc.) for the wireless business is booming and the carriers have money to spend. The entire wireless business model is based upon revenue generation since they charge for both minutes and data unlike the wired Internet. The next wave will be machine to machine communications since more accounts means more revenue for the networks. It is important to always know where the money is in a market. (Roos)
• There is a need to build both reconfigurable systems, like their single slot tester per device under test (DUT) systems, and to be able to reuse these system elements to lower overall costs. Chroma is also using the core elements to serve markets beyond ATE including solar cell testing, battery testing, and LED testing to further amortize development costs. (Chen)
• Mobile devices with wide I/O will be the next very high volume application which require stacked die using 3-D packing with through silicon vias (TSVs). However, for TSVs mechanical interconnects simply do not scale at this size. These products will ramp in 2013 but it is not clear when the test market for these devices will take off. (Loranger)
• Test continues to migrate to the wafer along with increased parallelism to maintain continued cost reductions (~30% per year). However for memory device these reductions are harder to achieve especially since the industry is already at one touchdown per wafer test. Test cell integration is the key to further reductions but needs a higher level of collaboration between industry and customers. (Loranger)

The panel fielded a number of questions from the audience – how to diversify beyond ATE, what to do about the hesitation from customers in regards to test cell integration, how to probe through silicon vias, ATE drivers for the next decade, and RF frequencies of interest. The panelists provided answers without the often anticipated controversies that make panel discussions exciting. There was some energetic follow up discussions immediately following the panel over drinks at the evening reception.

The second day program had six presentations in each of the two tracks for a grand total of twenty-six presentations. My only regret was the usual dilemma of which track to attend since there were many excellent presentation choices. The main program concluded mid-day with awards for the presenters. There were also two post-conference tutorials available that afternoon.

In summary, a small test focused event local in Silicon Valley (avoiding the time and expense of travel) well serves the industry especially with the abundance of expertise and potential participants. I look forward to many future editions of this conference!