IEEE Semiconductor Wafer Test Workshop – New Contact Technologies – Session One (Monday)

Here are the highlights from Session One – New Contact Technologies of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW)

Jay Kim, Western Specialty Technologies, LLC, “New Probe Card Architecture – Ceramic without MLC”:

He showed how Fine Instrument Co., Ltd.  (Korea) built a new probe card architecture which eliminates using multi-layer ceramics (MLCs) to avoid the cost and lead times issues.

They use a machined ceramic plate (“bulk substrate”) which holds daughter cards with a group (single site or more) of probes.  The daughter cards are the rigid part of a rigid-flex circuit with the flex portion providing the electrical connection to the Printed Circuit Board (PCB).  When asked he said the flex is soldered to the PCB to provide the best signal integrity.

Two examples probe card designs were shown:

  • CMOS Image Sensor – 32 test sites each with a light port through the probe card.
  • NAND FLASH – 300 mm full one touchdown with over 10K contacts and -40 to 90 C operating range.  Since their material has lower CTE than aluminum nitride and silicon nitride, it provides a greater operating margin over the entire temperature range.

John Hite, Texas Instruments, “Standardizing WSP-Wafer Socket Pogo Pin-Probe Cards”:

TI developed a standardized approach for testing Wafer Level Chip “Size” Packages (WLCSP) parts with solder bumps using spring pins (i.e. pogo pins) that they call Wafer Socket Probe (WSP).  By standardizing the foot prints of the probe heads on the PCBs, it allows them to decouple the design and fabrication of the probe heads from the design of the PCBs.  This also allows them to make the probe heads fully interchangeable so they can swap vendors or technologies especially since they have some parts they need to support for 20 years.

Traditional cantilevers and vertical probe technologies tend to damage the top of the bump.  By using crown tipped spring pins they reduce the damage to the bumps by only dimpling the sides of the balls. This reduces the downstream defects when reflowing the balls and hence avoids the need to reflow the balls to reshape them prior to solder attach.

Other advantages of this approach is they can put a lid on sockets and test singulated devices which avoid tying up production test cells to do bring up & engineering work.  In addition, since there is no X/Y/Z alignment adjustment they avoid the need for probe card metrology.

In terms of aligning the probe head to the PCB for 400 µm and greater pitch they use standard mechanical pin to hole alignment based upon PCB fabrication tolerance.  For <= 300 µm pitch they use a microscope to align the mechanicals by sighting a five dot fiducial pattern on the PCB.

With this approach they have done parts with 200 µm pitch and wide variety of applications from 16 sites with a total of 1,000 pins to a single flip chip part with 5,000 pins.

Bob Murphy, FormFactor, “Benefits of Flip Chip Wafer Sort using MEMs Multi Site Capability”:

Bob presented a paper written by Globalfoundries who had been looking for a better probe solution than current Cobra technology for testing flip chip wafers.  In general, they are motivated by the growth in the overall flip chip market (shown to be over $2B in 2012 in the TechSearch market data).  Another concern is the overall force required to probe a wafer as they double the number of sites to be tested in parallel.  FormFactor’s MEMS technology has a lower spring force (force versus deflection) than Cobra probes, so there is a substantial reduction in force as the probe count increases.

One notable finding is that when there is a lack of debris on the scrub mark the contact resistance (Cres) performance deteriorates.  It turns out the lack of debris is a sign that no cleaning is occurring as the probe is operating. This was found when investigating why the FormFactor card had lower initial performance then the existing vertical cards. The solution is to micro-step in the X-Y plane as the wafer is lowered from the probe tips (Z motion) in order to “self clean” the tips. They have reported a 16x increase in the number of touchdowns between cleanings by using this recipe. This is a good example of the typical “learning curve” issues that often happens when introducing new technology that requires engineering attention to resolve to root cause.

In terms of electrical performance, improvement is seen on tests that are extremely sensitive to contact quality.  In addition, some tests need to adjust timing due to change in electrical path.  In general, the MEMS probe cards have cleaner waveforms.

Note: I will post the link for the slides once they become available.

One Response to IEEE Semiconductor Wafer Test Workshop – New Contact Technologies – Session One (Monday)

  1. Michael L. says:

    Lots of interesting developments. Thanks for the concise updates

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