… and how it impacts your bottom line!
A poorly implemented semiconductor test cell may pass integrated circuit (IC) parts that are either defective or have marginal performance. They can cause the electronic devices in which they will be assembled to either malfunction or completely fail. However, two other conditions require evaluation. Having false negative test “escapes” is expensive in terms of final product test failures, warranty costs, customer dissatisfaction, etc. In turn, the false positive test escapes needs to be balanced against the cost of false negative failures where otherwise good parts fail the tests and are discarded. Test engineers, product managers, quality engineers, and operational managers needs to make either implicit or explicit decisions as to the proper balance in adjusting the test limits. The goal is to cost effectively approach “zero defects” without “throwing out the baby with the bath water”.
A test process generally categorizes the item or device being tested as “pass” or “fail”. Sometimes passing devices are graded (typically by speed or other desired quality) and failing devices are often grouped by failure mode. “Coverage” is how well a particular test process measures the functionality and specifications of a given device. If every feature and specification is tested then it is said to have 100% test coverage. However, exhaustive testing is usually expensive due to long test times which translates in to operational costs including the depreciation of the test system and greater test setup complexity (equipment and development cost). Sometimes complete coverage is not possible or practical so there needs to be a trade-off between coverage and cost.
Depending on the complexity of the device being tested, the test engineer(s) may spend several man-months setting up the automated test equipment (ATE) system and interface hardware along with writing software to properly test the devices. Interface hardware provides both the mechanical and electrical interface between the part being tested and the ATE system. Load boards (a printed circuit board with contactors or sockets to connect to packaged parts) and wafer probe cards (precisely placed probes which contact the electrical pads on the bare semiconductor wafer) are part of the interface hardware that typically needs to be developed and fabricated for each new design or design family. Whenever there is a change to the device or a problem is found with the test setup additional work is required to debug and modify the test program and/or the interface hardware.
Doing this setup work correctly and on time is critical to the successful introduction of a new IC since the test cell will determine how quickly the product can be “ramped up” to High Volume Manufacturing (HVM). For some high volume products millions of devices must be tester per month. Not only must the the test configuration be duplicated to hundreds of test cells (combination of ATE, interface hardware and materials handling equipment which function as a self-contained unit in the test area of the factory) but sophisticated software monitoring of failure and operational trends of the individual cells becomes an important tool.
In operation, the ATE presents different patterns of electrical signals to the device being tested and measures the response of the device. Sometimes this measurement is simply interpreted as a digital response (1 or 0) and other times a specific voltage or current is precisely measured. The sequence of patterns can be a few milliseconds long to several minutes depending on the complexity of the device and the overall test requirements. The greater the number of patterns run, the greater the test coverage within the capability of the ATE equipment. The test program specifies for each pattern what is an acceptable response (pass) or unacceptable response (fail).
Besides the issue of false positives and false negative a non-obvious issues is: What does a failure really indicate? The default assumption when a test or series of test fails is that the device being tested is bad. However that is not always the cause of the failure. Sometimes the ATE or interface hardware is intermittent or otherwise fails to faithfully deliver the electrical signal to the device or properly measure the devices response. For example, a wafer probe card for a dynamic random access memory (DRAM) device may have 20,000 or more probe tips all significantly smaller than a human hair distributed across a 300 mm wafer. These probe tips need to contact the device pads with exactly the right force and micron positional accuracy, often at elevated temperatures near 100 °C while simultaneously testing 200 to 300 memory parts. The failure of a single probe may cause one or more memory devices to fail. Once an unacceptable level of possibly good parts is discarded, the probe card needs to be replaced. In addition, the test cell needs to have the highest possible up-time to continuously test parts 7 x 24 for months on end for thousands of wafers with the absolute minimum of intervention or adjustment. The end result is that each and every test is testing not only the device but the entire test cell (ATE, test interface & material handler) and test program. Therefore, every element of the test cell needs to be engineered and built with the absolute highest quality and reliability to provide consistent and meaningful results.
Continuous improvement can be driven by data mining the enormous quantities of test result data to improve device yield (number of good parts passed). ATE typically logs the result of each and every measurement performed so that it can be analyzed either in real time or post processed (more typical). Test Engineers use statistical methods to do comparisons such as device to device, device to position on the wafer, wafer to wafer, lot to lot, tester to tester and factory to factory to identify any trends or slight deviations. How much is a 0.5% or 1% yield improvement worth to your product? At first, it may not appear to be worth the engineering effort required to achieve. However the impact on the product line can be substantial in terms of additional shippable products and reduced waste especially for a high volume product.