IEEE Semiconductor Wafer Test Workshop – Probe Potpourri – Session Seven (Tuesday)

Here are the highlights from Session Seven – Probe Potpourri of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 8th.

Boyd Daniels, Texas Instruments, “Very Low Cost Probe Cards – A Two Piece Approach”:

For their “catalog” parts – medium complexity, low volume, and medium number of devices – historically it has been cheaper to blind package (i.e. skip wafer test prior to packaging) and take the yield loss at package test.  The main issue is the high initial cost and maintenance of probe cards is too high relative to the volume of parts to be tested.

If the cost for a single site probe card is less than $1,000, then it would make sense to do wafer testing on catalog parts.  In order to keep the cost low, they revisited a previous two piece probe card approach where there is a “mother board” common to a family of parts and a “daughter board” specific to the individual part with the cantilever needles attached.  This previous approach failed due to several issues however the main weaknesses were the high cost of the custom connector between the mother board and daughter boards and it was too difficult to planarize the probes to the wafer after each change of the daughter card.  The latter issue was due to the mother board being the reference surface for setting the planarity of the probes.

Working with Millennium Circuits, they developed new approach based on a two piece scheme.  The mother board still holds the family circuitry but connects to the daughter cards with a spring pin tower (i.e. “pogo” ring).  This avoids the need for an expensive connector on each daughter card.  And the reference surface was moved to the daughter card to solve the planarity issues. Cutouts on the daughter card allow components on mother board (family board) to protrude as required.

In addition, they added self-imposed constraints to keep testing to less than $0.01 per part:

  • Low needle count – reduces the force and eliminates the need for mechanical stiffeners
  • Family of parts required prior to building probe cards
  • No multisite testing allowed

They have successfully implemented this approach on their very low cost tester (VLCT) platform [TI proprietary test system] and they are looking at other test platforms.

Anil Kaza, Intel Corporation, “Metrology and Probe Repair challenges with tighter pitch probe cards”:

As the probe count increases and the probe pitch decreases, Intel’s challenges at Probe Card Metrology or Maintenance (PCM) are increasing due to the very high mix of testers and volume of probe cards.  Their most challenging issue at PCM is that the current probe card metrology tools have issues with the optical recognition of the probe tips and related image processing recipes.

As the probes decrease in size and the pitch tightens the optical recognitions problems get worse further decreasing the throughput of the metrology tools. These issues are also complicated due to the wide range of probe technologies in use at Intel and the requirement to remain repeatable and reliable over time.

In terms of probe repair, adjusting probe position (i.e. plastically deforming probes back to their desired target position) is also becoming harder as both the probe size and the probe pitch decrease. Currently they are not using their metrology tools for probe adjustment due to ergonomic concerns (the stage is not height adjustable).  So they make their adjustments off the metrology tool and then need to bring the card back to the metrology tool to check the adjustment.  They then iterate between the metrology tool and the adjustment tool as required until all the probes are in specification.

They have build a proof of concept tool to assist with the probe adjustment using a dual camera video system that merges the image of a reference glass mask and the image of the probe array  being adjusted.  This allows the operator to see which tips need adjustment and to check the adjustment as it is being performed. They are also working on an electronic “overlay” system video system where the reference image is generated by computer and superimposed on the video image of the probes.  However, properly synchronizing the images has proven to be challenging.

In addition, as the probes become smaller it has become more difficult to manually manipulate (deform) them.  They are investigating a number of semi-automatic and automatic micromanipulators and micro-tweezers to assist with the adjustment process.

Using the video system and tools to assist with adjustments they are implementing a station to perform real time qualitative verification of probe adjustment. They will then know the probes are in proper position prior to running the card on the metrology tool which will also check electrical parameters of the probe card in addition to the positional checks.

Intel prefers that suppliers and vendors engage proactively to address these metrology challenges. New suppliers of probe cards will need to provide a total approach including repair/maintenance capabilities.

Hiroyuki Kamibayashi, Mitsubishi Cable Industries, Ltd., “Ultra Low Leakage Probes & Cables For Fine Pitch Probe Cards”

Mitsubishi Instrument Component Division’s MEXCEL coating process electro-deposits polyimide to be used as an insulator on metals.  Then they use either a laser or a solvent to remove the coating to expose the conductor as required for interconnect.  As an example and probably of greatest interest to the audience, Kamibayashi-san showed probes that were processed this way – body section insulated with the polyimide but with exposed tips on each end of the probe. The process can deposit polyimide 1 to 100 µm thick with better than 5% uniformity without bubbling or pin holes.

Another product shown from Mitsubishi’s Cable Division was ultra miniature coaxial cables in two versions:

  • 210 µm outer diameter with 50 ohm impedance
  • 810 µm outer diameter low loss cable (2.6 dB/m @ 2 GHz)

Terence Q. Collier, CVInc, “Overpad Metallizations and Probe Challenges”:

Root cause of wire bonding issues are the same as probe issues. If you make it better for bonding, you will make it better for probing. By eliminating the aluminum oxide or corrosion layer, probing should improve (better contact).

Terrance is suggesting either an improved wafer cleaning (wet) process or to change the pad metal from Al to electro-less nickel gold (ENIG) with palladium (ENIPIG).  With ENIG, the nickel will bleed in to gold so ENIG alone simply changes the corrosion on the pad surface.  Adding the palladium avoids the electro migration – hence the recommendation for ENIPIG.  The 0.03 to .06 µm Au flash on top prevents the palladium from oxidizing. Included in the presentation are the results of the wire bond study (images and data) using ENIPIG along with scanning electron microscope (SEM) images of the oxide formations typically seen.

Note: I will post the link for the slides once they become available.

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