After a gloomy first session focused on world economics at SEMI Industry Strategy Symposium (ISS) 2012, Session 2 – Semiconductor Markets was significantly more upbeat.
Stephen G. Newberry (Vice Chairman of the Board, Lam Research Corporation) started off with a way forward in Read the rest of this entry »
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2.5D/3D Stacked Integrated Circuits (ICs), 450 mm wafers, Economics, Moore's Law, SEMI, Semiconductor Capital Equipment (CAPEX), Semiconductors | 
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Posted by Ira Feldman
Like the roller coaster ride that is the semiconductor industry, the SEMI Industry Strategy Symposium (ISS) 2012 had its share of ups, downs, twists, and turns. Semiconductor Equipment and Materials International – better known as SEMI – as the industry association of suppliers to semiconductor manufacturers has held this annual conference in early January for thirty five years to provide updates on business conditions and technology roadmaps to enable SEMI members to plan for the coming year. The conference was packed with senior management paying close attention to the industry leaders, analysts, and customer presenters. All of the presentations, even the most poorly disguised sales pitch or infomercial, contained several valuable insights.
In his keynote presentation “Technology Law Still Delivers“, William Holt (Senior Vice President; General Manager, Technology & Manufacturing Group, Intel Corporation) opened the conference with much optimism based upon Read the rest of this entry »
Leave a Comment » | Economics, SEMI, Semiconductor Capital Equipment (CAPEX), Semiconductors | Permalink
Posted by Ira Feldman
…To make sense of the big picture, one needs to follow the money and then head to China.
Ed Pausa the primary author of PricewaterhouseCooper’s (PwC) recently published report “Continued Growth: China’s Impact on the Semiconductor Industry – 2011 Update” provided an overview at this month’s MEPTEC luncheon. His presentation was a helpful tour to start digesting this impressive report, now it its seventh annual update. The report runs 112 pages in length and is packed with figures, data and most importantly analysis. Building a cohesive picture from many disparate data sources is a major undertaking and PwC should be applauded for making available this excellent work.
After listening to this presentation and reading the report, I find two items that really stand out as primary market forces. Unraveling the convoluted web of the semiconductor supply chain to examine these items will lead to greater understanding of the industry. They are, Read the rest of this entry »
Leave a Comment » | Marketing, MEPTEC, Semiconductor Capital Equipment (CAPEX), Semiconductors | Permalink
Posted by Ira Feldman
At this time of year, when my children see a box arrive they immediately question if it is another present for them. They are very disappointed when the Amazon.com box contains breakfast cereal or dish detergent. They are definitely thinking inside the box. If the box is large enough, they will eventually start playing in it and imagine it is not a box.
Childrens’ imagination has no bounds. Adults need to make conscious efforts to think outside the box as this can Read the rest of this entry »
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Posted by Ira Feldman
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Back for the second year (with a minor name change), the Silicon Valley Test Workshop is an unpolished gem. Looking past the rough edges (minor logistical issues), what really shines through is the interaction of the participants. This conference really has Read the rest of this entry »
Leave a Comment » | 2.5D/3D Stacked Integrated Circuits (ICs), Automatic Test Equipment (ATE), Load Boards, Moore's Law, More than Moore, My Presentations, Packaging (Semiconductor), Printed Circuit Boards (PCB), Probe Cards, Semiconductor Test, Test Engineers, Through-Silicon Vias (TSV), ToThePoint | Permalink
Posted by Ira Feldman
The MEPTEC “2.5D, 3D and Beyond – Bringing 3D Integration to Packaging Mainstream” conference was a mixed-bag. Yes, it is always exciting to hear about new suppliers and progress. But it is disconcerting to realize that the price of progress is an ongoing burden on our industry’s supply chain.
Subramanian Iyer (IBM) and Theresa Sze (Oracle) started with Read the rest of this entry »
Leave a Comment » | 2.5D/3D Stacked Integrated Circuits (ICs), Manufacturing, MEPTEC, Packaging (Semiconductor), Probe Cards, Semiconductor Test, Semiconductors, Through-Silicon Vias (TSV) | Permalink
Posted by Ira Feldman
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The MEMS Testing and Reliability 3rd Annual Conference gets high marks: excellent speakers focused on an emerging topic and it was large enough to have “critical mass” while allowing everyone to interact. It was well produced by MEMS Investor Journal and MEPTEC.
My presentation, “Semiconductor Wafer Test Technology and Trends: Lessons for MEMS Test Engineers“, covered the differences between testing semiconductors and microelectromechanical systems (MEMS). I reviewed the progress in test technology over the last fifty plus years, from simple cantilever probe cards to large full wafer contact probe cards, developed to reduce the cost of test.
I discussed lower cost solutions that appear counter-intuitive since they require increased technical and operational complexity. Challenges of testing MEMS devices while still on wafer (prior to packaging and singulation) were discussed along with a review of MEMS solutions at this year’s IEEE Semiconductor Wafer Test Workshop.
With the proper skills, experience, and perspective it is possible to avoid “re-inventing the wheel” and to develop the best strategy to profitably introduce new technologies to high volume manufacturing.
Leave a Comment » | MEMS, MEMS Investor Journal, MEPTEC, My Presentations, Operations, Product Management, Semiconductor Wafer Test Workshop, Test Engineers | Permalink
Posted by Ira Feldman
Here are the highlights from Session Nine – “Productivity / COO” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 15, 2011.
Doron Avidar, Micron, “Ghosting – Touchdown Reduction Using Alternate Site Sharing“:
Even though memory testers can support very high parallelism, with smaller memories (in terms of capacity and dimensions) there are more die per wafer requiring Read the rest of this entry »
Leave a Comment » | CMOS Imagers, FLASH Memory, IEEE, Multi Layer Ceramics (MLC), My Presentations, Operations, Photolithography, Printed Circuit Boards (PCB), Probe Card Metrology Tools, Probe Cards, Product Management, Semiconductor Wafer Test Workshop, Space Transformers | Permalink
Posted by Ira Feldman
Here are the highlights from Session Eight – “RF Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 15, 2011.
Seenew Lai, MPI, “High Bandwidth (>2.5 Gbps) and Fine Pitch (< 30 µm) Cantilever Probe Card“:
The data rate of liquid crystal display (LCD) drivers are increasing to the point that traditional cantilever probe cards cannot support the required bandwidth. Using electromagnetic simulation it was determined Read the rest of this entry »
Leave a Comment » | High Frequency (RF) Testing, IEEE, Printed Circuit Boards (PCB), Probe Cards, Semiconductor Wafer Test Workshop | Permalink
Posted by Ira Feldman
Here are the highlights from Session Seven – “High Temp / Extreme Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 14, 2011.
Kevin Fredriksen, SPA GmbH, ”MSO – Multi-Site Optimizer”:
Most wafer probers do not supply intelligent stepping algorithms to calculate the most efficient sequence of moving the wafer relative to the probe card. (Ed: At the core of this is a traveling salesman problem.) The situation is exacerbated when Read the rest of this entry »
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Posted by Ira Feldman
Here are the highlights from Session Six – “Probe Potpourri” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 14, 2011.
Marc Knox, IBM, “The Development of a Flexible and Efficient Chip Thermal Imaging Capability“:
Traditional burn-in systems hold multiple printed circuit boards (PCBs) with one or more devices in burn-in sockets to provide temporary electrical interconnect to a device under test (DUT). These PCBs and sockets are known as “burn-in boards”. And the systems in which they are loaded are “ovens” that permit temperature stressing, sometimes at both hot and cold temperatures, while stimuli are supplied to the chip. The purpose of “burning-in” a device is to screen for infant mortality in an accelerated manner.
The IBM team adapted a burn-in board system to Read the rest of this entry »
Leave a Comment » | 3-D Microstructures, IEEE, Packaging (Semiconductor), Probe Cards, Semiconductor Wafer Test Workshop, Space Transformers | Permalink
Posted by Ira Feldman
Here are the highlights from Session Five – “Spring Pin Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 14, 2011.
Brandon Mair, Texas Instruments, “WSP-Wafer Socket Probe for Flip Chip Applications“:
Wafer socket probe (WSP) technology has demonstrated better physical and electrical performance and lower cost of ownership (COO) than traditional vertical probe cards for testing wafer level chip scale packages (WLCSP) at 0.4 mm (400 µm) pitch. These WSP probe heads are typically built Read the rest of this entry »
2 Comments | Cost of Test, IEEE, Probe Cards, Semiconductor Capital Equipment (CAPEX), Semiconductor Test, Semiconductor Wafer Test Workshop | Permalink
Posted by Ira Feldman
Here are the highlights from Session Four – “High Performance Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.
Bob Davis, Rudolph Technologies, “Testing Probe Cards That Contain Complex Circuitry“:
Over time, probe cards have increased in complexity from simple wire cantilever probes to those including passive components and digital control circuits. Some of these digital control circuits may even contain state based logic. At the same time the physical complexity of probe cards have increased in probe and channel counts, probe density, and total probe force. As a result, Read the rest of this entry »
Leave a Comment » | 2.5D/3D Stacked Integrated Circuits (ICs), DRAM, More than Moore, Packaging (Semiconductor), Probe Card Metrology Tools, Probe Cards, Semiconductor Test, Semiconductor Wafer Test Workshop, Through-Silicon Vias (TSV) | Permalink
Posted by Ira Feldman
Here are the highlights from Session Three – “Power Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.
Michael Huebner, FormFactor, “A Hot Topic: Current Carrying Capacity, Tip Melting and Arcing”:
Power consumption per dynamic random-access memory (DRAM) is increasing to as high as 400 mA or more under normal test conditions. At the same time the number of DRAMs being tested in parallel – and sharing the same power supply – is increasing. Therefore, the risk of current damage to probes is increasing.
Two distinct, but related concerns are Read the rest of this entry »
Leave a Comment » | DRAM, IEEE, Memory Technology, Probe Card Metrology Tools, Probe Cards, Semiconductor Test, Semiconductor Wafer Test Workshop, Simulation | Permalink
Posted by Ira Feldman
Here are the highlights from Session Two – “Optimization / Process Analysis” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.
Steven Ortiz, Avago, “Probe to Pad Placement Error Correction for Wafer Level S-Parameter Measurements”:
Avago’s film bulk acoustic resonators (FBAR) technology usage is being expanded from filters to include oscillators. The example oscillator discussed operates at a 1.5 GHz resonant frequency with a Quality (Q) factor ranging from one thousand to several thousand and a one year aging specification of less than 25 ppm.
These devices are extremely difficult to test due to their precision and small size (not much larger than the two device pads). The drift specification is the hardest to measure. Since it is generally desirable to have at least 10x measurement capability, the drift measurement requires approximately 2.5 ppm of tester performance, i.e. 3.75 KHz accuracy at 1.5 GHz. They use Read the rest of this entry »
Leave a Comment » | High Volume Manufacturing (HVM), IEEE, Management, MEMS, Operations, Probe Cards, Quality, Semiconductor Test, Semiconductor Wafer Test Workshop, Statistical Process Control (SPC), Yield Improvement | Permalink
Posted by Ira Feldman
