April 11, 2013
Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Spring 2013 edition on page 14-15.
Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column by mixing technology and general observations is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.
Measuring Up
Tap to turn on. Wait for it to zero. Step on. I haven’t lost any weight, still 205 pounds even with all this exercise and careful eating? Step off, step back on. 212 pounds. Damn, wrong answer. Step off, step back on. 206 pounds. Okay maybe the first reading was right. Optimistically record 205 pounds. Does this nightly dance sound familiar? Not only are bathroom scales the bearer of bad news, their Read the rest of this entry »
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Bioscience, Coupling & Crosstalk, Healthcare, Internet of Things, Medical Devices, MEMS, MEPTEC | Tagged: Bioscience, Coupling & Crosstalk, Healthcare, Internet of Things, Medical Devices, MEMS, MEPTEC | 
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Posted by Ira Feldman
March 14, 2013
Sunset over Phoenix, Arizona during BiTS Workshop
As the Burn-in & Test Strategies (BiTS) Workshop 2013 fades into the sunset (queue the music), here is a round-up of the highlights. There were gun fights in the corral as well as technical questions for the presenters. The saloon girls and gunfighters took an edge off of the “geek” factor. This year over three hundred fifty people come to the “Circle BiTS Ranch” (aka the Hilton in Mesa, Arizona) for the premier conference focused on what is new and next for semiconductor test tooling and strategy. Oh, did I mention that the theme this year was Western?
This was the 14th annual BiTS Workshop, which has achieved the perfect conference trifecta of Read the rest of this entry »
Leave a Comment » | BiTS Workshop, Cost of Test, DRAM, Interconnectology, Load Boards, Memory Technology, Moore's Law, More than Moore, My Presentations, Packaging (Semiconductor), Printed Circuit Boards (PCB), Probe Cards, Semiconductor Capital Equipment (CAPEX), Semiconductor Test, Semiconductors, Spring Pins, Test Engineers | Tagged: BiTS Workshop, Cost of Test, DRAM, Interconnectology, Load Boards, Memory Technology, Moore's Law, More than Moore, My Presentations, Packaging (Semicondcutor), Printed Circuit Boards (PCB), Probe Cards, Semiconductor Capital Equipment (CAPEX), Semiconductor Test, Semiconductors, Spring Pins, Test Engineers | Permalink
Posted by Ira Feldman
January 22, 2013
Intel shows first fully patterned 450 mm semiconductor wafer at SEMI ISS 2013
Attending the SEMI Industry Strategy Symposium (ISS) is like drinking from a fire hose with the additional risk of whiplash. Don’t get me wrong, it is an exquisite fire hose but sometimes the data presented can be overwhelming at this conference of semiconductor supply chain executives. The majority of the attendees and presenters are executives from the SEMI member companies that develop the equipment, materials, processes, and technology used to build, test, and package semiconductors. And the executives present from the semiconductor manufacturers are typically the “end customers”.
The greatest value of SEMI ISS, beyond the networking, is the strategic overview of the entire semiconductor ecosystem. What are the market drivers, the technology needed, and the roadmap status of this industry? It is true that we all know where we need to head courtesy of Moore’s Law and the International Technology Roadmap for Semiconductors which attempts to keep us on that trajectory. The pressure of consumers needing wanting greater functionality at lower costs is relentless. Much of the technological detail of this ecosystem is addressed in a myriad of other forums throughout the year. ISS ties these technical requirements, development needs, and business needs back to the strategic direction and desires of the global marketplace.
The whiplash comes from Read the rest of this entry »
Leave a Comment » | 2.5D/3D Stacked Integrated Circuits (ICs), 450 mm wafers, Automatic Test Equipment (ATE), Fabs, Healthcare, High Volume Manufacturing (HVM), International Technology Roadmap for Semiconductors (ITRS), Management, Market Analysis, Moore's Law, SEMI, Semiconductor Capital Equipment (CAPEX), Semiconductor Test, Semiconductors | Tagged: 2.5D/3D Stacked Integrated Circuits (ICs), 450 mm wafers, Automatic Test Equipment (ATE), Fabs, Healthcare, High Volume Manufacturing (HVM), International Technology Roadmap for Semiconductors (ITRS), Management, Market Analysis, Moore's Law, SEMI, Semiconductor Capital Equipment (CAPEX), Semiconductor Test, Semiconductors | Permalink
Posted by Ira Feldman
January 1, 2013
As we bid adieu to 2012, I realize that I have been remiss in providing updates on all of the exciting activity since my last one in May. I will rectify this situation below and have added regular updates to my list of New Year’s resolutions.
Challenges
In May, it was great to see the many responses to the Big Hairy Audacious Goal where Janusz Bryzek (Fairchild Semiconductor) challenged the microelectromechanical systems (MEMS) industry at the MEMS Technology Symposium that I described in “Thinking Big: $1 Trillion MEMS Market” (part 1 and part 2).
In June, I reviewed the test challenges of the transition to 450 mm semiconductor wafers with my presentation “The Road to 450 mm Semiconductor Wafers” at the IEEE Semiconductor Wafer Test Workshop (SWTW). I have posted summaries of this entire excellent workshop: keynote and sessions 1, 2, 3, 4, 5, 6, 7, 8, and 9.
In one very hectic July week, I attended the summer working meeting of the International Technology Roadmap for Semiconductors (ITRS), the SEMICON West trade show, and the Test Vision 2020 conference. The focus of Read the rest of this entry »
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Posted by Ira Feldman
December 31, 2012
Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Winter 2012 edition on page 12-13.
Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column by mixing technology and general observations is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.
Quality for the Long Haul?
Does a manufacturer’s responsibility and interest in quality end when the warranty expires?
When is death premature? People have life expectations based upon family and societal statistics as well as their health. Mechanical devices, especially those with moving parts, have estimated lives and known wear out mechanisms. Cars currently have an average age of 11 to 13 years of useful life which allows consumers to set reasonable expectations of service life. What about electronics? What is a reasonable expectation of service life?
I had a few devices at home fail recently which makes me wonder about Read the rest of this entry »
1 Comment | Coupling & Crosstalk, Economics, MEPTEC, Quality | Tagged: Coupling & Crosstalk, Economics, MEPTEC, Quality | Permalink
Posted by Ira Feldman
December 19, 2012
Lego Blocks (flickr: antpaniagua)
My event summary recently published in Chip Scale Review Tech Monthly:
Is 3D semiconductor packaging really the Lego of the integrated circuit (IC) world? It is a great analogy for the range of possible solutions and flexibility provided by different flavors of 3D packaging (2.5D on interposer, 3D, 5.5D, etc.) and “colors” (homogenous and heterogeneous) of die stacks. Plenty of pictures of Legos and scanning electron microscope (SEM) images were shown last week at the RTI International Technology Venture Forum symposium and conference “3-D Architectures for Semiconductor Integration and Packaging”. Presenters clearly articulated the great promise of what could be built with 3D packaging. At the same time, progress towards solving the multitude of challenges to make this technology as pervasive, if not as easy to use and fun, as Legos was discussed.
The challenges span Read the rest of this entry »
Leave a Comment » | 2.5D/3D Stacked Integrated Circuits (ICs), Chip Scale Review, CMOS Imagers, DRAM, Fiber Optic Interconnect, Packaging (Semiconductor), Semiconductor Test, Semiconductors, Standards, Through-Silicon Vias (TSV) | Tagged: 2.5D/3D Stacked Integrated Circuits (ICs), Chip Scale Review, CMOS Imagers, DRAM, Fiber Optic Inteconnect, Packaging (Semicondcutor), Semiconductor Test, Semiconductors, Standards, Through-Silicon Vias (TSV) | Permalink
Posted by Ira Feldman
December 6, 2012
Can reliability and production testing keep pace with the explosive growth in microelectromechanical system (MEMS) based product volumes? Soon it will be the rare consumer product that does not include a MEMS device bringing us closer to the possibility of a $1 trillion MEMS market. In order to achieve greater adoption of the technology, cost and quality goals will need to be met through testing and reliability. This was the focus of the MEMS Testing and Reliability 2012 conference produced by MEMS Journal and MicroElectronics Packaging and Test Council (MEPTEC).
Session 4
Mervi Paulasto-Kröckel (Professor, Aalto University) in “On the Reliability Characterization of MEMS Devices” examined the current methods for reliability assessment in MEMS devices and identified necessary improvements. Currently, the reliability of MEMS devices are evaluated in the functioning state. A sensor is tested by applying a known stimulus and comparing the sensor output while varying the test conditions such as temperature, humidity, etc. MEMS actuators are similarly tested by providing a known input and measuring the output of the actuator over the range of test conditions. Significant deviation between the expected and measured result indicates a failure. Simple functional test is appropriate for manufacturing quality testing however it is inadequate for measuring and improving device reliability.
Professor Paulasto-Kröckel compared these processes commonly used to estimate MEMS reliability to those used in the microelectronics industry. She identified major methodology changes required Read the rest of this entry »
Leave a Comment » | High Volume Manufacturing (HVM), MEMS, MEMS Journal, MEMS Test, MEPTEC, Microfabrication, Nanotechnology, Reliability | Tagged: High Volume Manufacturing (HVM), MEMS, MEMS Journal, MEMS Test, MEPTEC, Microfabrication, Nanotechnology, Reliability | Permalink
Posted by Ira Feldman
