MEMS Testing and Reliability 2012 – Session 3

Can reliability and production testing keep pace with the explosive growth in  microelectromechanical system (MEMS) based product volumes? Soon it will be the rare consumer product that does not include a MEMS device bringing us closer to the possibility of a $1 trillion MEMS market. In order to achieve greater adoption of the technology, cost and quality goals will need to be met through testing and reliability. This was the focus of the MEMS Testing and Reliability 2012 conference produced by MEMS Journal and MicroElectronics Packaging and Test Council (MEPTEC).

 

Session 3

Pavan Gupta (Vice President of Operations, SiTime) provided a cautionary tale in “Packaging and Reliability Qualification of MEMS Resonator Devices”. Historically many MEMS companies have failed to start the device and package co-design as early as possible even though packaging was upwards of 80% of the product cost. [Perhaps they aren’t really using a concurrent engineering methodology?] Even though the cost of packaging has dropped significantly, the complexities and risks related to packaging remain high.

There are many challenges related to MEMS packaging since without a reliable and qualified package, it is not possible for one’s customers to easily and confidently integrate a MEMS product into their end product. In SiTime’s case they had a double challenge of Continue reading “MEMS Testing and Reliability 2012 – Session 3”

MEMS Testing and Reliability 2012 – Session 2

Can reliability and production testing keep pace with the explosive growth in  microelectromechanical system (MEMS) based product volumes? Soon it will be the rare consumer product that does not include a MEMS device bringing us closer to the possibility of a $1 trillion MEMS market. In order to achieve greater adoption of the technology, cost and quality goals will need to be met through testing and reliability. This was the focus of the MEMS Testing and Reliability 2012 conference produced by MEMS Journal and MicroElectronics Packaging and Test Council (MEPTEC).

Session 2

Mårten Vrånes (Director of Consulting Services, MEMS Journal) in “A Test-centric Approach to MEMS ASIC Development” discussed alternatives to the traditional co-design of the MEMS element and application specific integrated circuit (ASIC). As many MEMS devices require an ASIC to control and/or sense the MEMS element the most logical approach is to design both parts in parallel. However the scope of such a development effort is often beyond the resources – both in terms of talent and funding – for many companies especially startups.

Mr. Vrånes started with the challenges and pitfalls of ASIC development for MEMS devices. There are challenges regardless of Continue reading “MEMS Testing and Reliability 2012 – Session 2”

MEMS Testing and Reliability 2012 – Session 1

It was my pleasure to attend the MEMS Testing and Reliability 2012 conference to see the considerable progress made in these areas as microelectromechanical system (MEMS) based product volumes accelerate. We may soon get to the point where it will be the rare consumer product that does not include a MEMS device bringing us closer to the possibility of a $1 trillion MEMS market. But in order to achieve greater adoption of the technology, cost and quality goals will need to be met through testing and reliability, the focus of this conference produced by MEMS Journal and MicroElectronics Packaging and Test Council (MEPTEC).

Session 1

Mario Correa (MEMS Test Engineering Manager of Fairchild Semiconductor) started with “Evolution of MEMS Test Solutions” reviewing how test equipment and processes have evolved from the 1960’s to today. There have been major changes to test methods developed for non-MEMS sensors first used with military and aerospace MEMS sensors in the late 1960’s where the annual volume was measured in thousands of units to those used today for over three billion units shipped yearly to the consumer electronics market. It has been a challenge keeping up with the high triple digit growth rates from 2009 to 2012 including gyroscopes +189%, microphones +347%, and digital compasses +778%. MEMS accelerometers grew “only” +78% during this period. (Growth data per Yole)

These changes include Continue reading “MEMS Testing and Reliability 2012 – Session 1”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 9 (Wednesday)

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Here are the highlights from Session Nine “Productivity / Cost of Ownership (COO)” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 13, 2012.

Teruyuki Kitagawa (Nomura Plating, Co., Ltd. – Japan), “Unique Characteristics of the Novel Carbonaceous Film with High Electrical Conductivity and Ultra High Hardness for Semiconductor Test Probes”:

In a follow-up to last year’s presentation, improvements to Nomura’s carbonaceous film were discussed. The film has a much higher hardness (Hv 4000) than palladium (Pd, Hv 350 ~ 400) or even diamond-like carbon (DLC, Hv 1000 ~ 2000) which provides wear resistance and acts as a self cleaning surface. The significant improvement since last year is  Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 9 (Wednesday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 8 (Wednesday)

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Here are the highlights from Session Eight “Probe Process and Metrology” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 13, 2012.

Rob Marcelis (BE Precision Technology ‐ The Netherlands), “H3D Profiler for Contact Less Probe‐Card Inspection”:

Probe cards require inspection since they are consumables subject to wear. Changes in probe position or shape can damage the semiconductor devices they are testing. As probe cards increase in size and probe count, the probe cards themselves are becoming more expensive to test in terms of test time and complexity. Each new test system typically requires an expensive “motherboard” for the probe card metrology tool to simulate the mechanics of the tester and provide electrical interconnect to the card for electrical testing.

BE Precision Technology took a different approach by Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 8 (Wednesday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 7 (Tuesday)

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Here are the highlights from Session Seven “Fine Pitch Probing Challenges” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 12, 2012.

Jose Horas (Intel Mobile Communications ‐ Germany), “28nm Mobile SoC Copper Pillar Probing Study”:

Intel Mobile Communications (IMC, previously Infineon Wireless) has started to switch from tin-silver (SnAg) solder bumps to copper pillars (CuP) with SnAg caps for attaching their die to packages. Since the bumps and pillars are formed on the wafer prior to testing of the devices the wafer probe process must accommodate both. CuP offer several advantages over SnAg bumps: tighter pitch (now at 120 µm and able to scale smaller versus 150 µm for SnAg bumps), lower substrate costs due to relaxed design rules, and lower assembly costs (easier to under fill).

The MicroProbe Apollo (vertical buckling beam) probe cards optimized for low force probing using 2.5 mil diameter probes were  Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 7 (Tuesday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 5 (Tuesday)

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Here are the highlights from Session Five “New Probe Card and Contact Technologies” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 12, 2012.

Tsutomu Shoji (Japan Electronics Materials Corp. ‐ Japan) and Takashi Naito (Advantest ‐ Japan), “Full Wafer Contact Breakthrough with Ultra‐High Pin Count”:

Awarded Best Overall Presentation

As the number of probes on probe cards increase due to greater parallelism, driven by the desire for one touchdown testing and the future transition to 450 mm wafers, the total force required to probe a wafer increases if there is no reduction in the force per probe. This wafer prober chuck needs to apply the required force by pushing the wafer against the probe card typically held in place by the structure of the prober. With 200K probes on a 450 mm wafer each requiring 5 gF this is approximately equal to 1 ton (2205 lbF) of applied force. To reduce these force requirements wafer chuck and prober structure, Advantest and JEM have Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 5 (Tuesday)”