Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.
Known Good Die (KGD) – Is this a case of “everything old is new again” or acid reflux from a mature semiconductor industry? Today there is a greater need than ever to know that a given semiconductor die is good before proceeding to package it. This particular quest for the holy grail has provided plenty of challenges and indigestion to test engineers, packaging engineers, and product manager alike. Through the years some have even argued that KGD are unobtainable.
The bottom line is that KGDs are important to your business! KGDs are essential to make today’s advanced packaging economical. With the demise of Moore’s Law, the complexity of advanced packaging will increase as companies innovate. As a community of electronics professionals, we need to come together to determine “what is good?” and “how good is good enough?” We need to restart the debate on the necessity of KGD since it will ultimately improve our tools and processes to economically delivery quality die. Now is the time to revitalize the discussion at the 20th anniversary MEPTEC KGD Workshop on December 12,2019!
Not convinced of the importance of KGD? Let’s start with a history lesson and apply the concepts to today’s packaging…
In the ‘old days’ the integrated circuit (IC) manufacturing flow was relatively simple: Wafer Probe followed by Packaging and then Functional (often called “Final”) Test. Wafer Probe checked for basic functionality of the IC die to screen out gross failures and to determine if a given die is worth packaging. Functional Test not only tested that the die was assembled correctly in the package but that it met the desired performance characteristics. If device burn-in was required to reduce infant mortality, this was performed using the packaged parts followed by another Functional Test pass to screen out devices that failed prematurely.
In the 1980 & 90s there was a lot of interest in KGD as packaging technology was pushed hard for high performance solutions. The demand for KGD grew in proportion to the rising cost of this high-performance packaging technology – everything from central processing unit (CPU) packaging to multi-chip modules (MCMs). At the time, there were empty CPU packages costing almost as much as the CPU die itself due to increasing clock speeds and thermal management requirements not to mention an increased number of connection ‘pins’. And MCMs were being used to build complex system modules using more than one die. I.e. to provide functionality greater than what could be built as a single die. Many of these advanced packaging challenges faded away, removing the demand for KGD, when advanced process nodes permitted architectural solutions like multi-core CPUs to solve the performance needs.
Resurgence of complex packaging solutions have reappeared as the economics of Moore’s Law have been exhausted. The cost of the latest IC fabrication process nodes with finer geometries have increased exponentially. Therefore, die shrinks using these newer process
nodes to produce a smaller integrated circuit (IC) are no longer providing a cost savings. In the new era of “More than Moore”, companies are turning to advanced packaging to provide differentiated solutions.
These new types of packaging include an alphabet soup of acronyms including WLCSP, FiWLCSP, FoWLCSP, 2D, 2.5D, 3D, PLP, and more. It seems like a new packaging technology or a variant is announced weekly. Many of these solutions involve multiple die which screams for KGD since a single bad die renders the entire package as junk.
Even the simplest (and earliest) of these packaging solutions, Wafer Level Chip Scale Packaging (WLCSP) and the Fan-in (Fi) variation, give test and quality engineers cause for concern. These are both single-die chip scale packaging (CSP) where the “packaging” is processed directly on the wafer. The wafer is taken from the IC fabrication line and has electrical redistribution layers (RDLs) applied. The RDL scale up the electrical connection from the die pitch to printed circuit board (PCB) pitch. A solder ball is then placed on each output pad in the BGA. The Functional Test is done by contacting these solder balls to provide the necessary electrical connections.
What is different about these WLCSP parts is that the singulation – cutting, dicing, or cleaving the wafer into individual dies – is done AFTER the solder balls have been placed and the parts have been tested while still on the wafer. This is unlike the traditional process flow where the only thing done after Functional Test on the singulated packaged part is a last optical inspection for cosmetic issues and placing the parts into shipping containers. Test engineers then rightfully ask: how do we know nothing has happened to the part after the “final” test? Did the singulation crack or otherwise damage the part?
Due to the high cost of test, including the challenges in handling many small WLCSP parts, it is not economical to do another Functional Test after singulation. Even with special electrical test structures, it is difficult to detect and find cracking or other physical damage to the die unless there are gross failures. Therefore, advanced optical and x-ray inspections have been added to the final inspection process for these parts. For higher value parts, or those with higher reliability requirements, a Functional Test and possibly Burn-in may still be in order after the singulation even with the resultant increase in cost. As ‘packaged parts’ WLCSPs would no longer considered to be die. Let alone Known Good Die.
Fan-out WLCSP (FoWLCSP) and Panel Level Processing (PLP) use similar core manufacturing processes to WLCSP. However, both packaging processes transfer die from the original wafer to a carrier substrate making high quality die essential. “Good” die are selected after test and singulation from their original wafer and moved to carrier (wafer or panel). They are spaced further apart to accommodate “fan-out” of the RDL so ultimately the solder balls array is larger than the die size. Optionally, if spaced far enough apart additional dies and passives can be placed on the carrier and interconnected by the same RDL. This allows multiple die to be contained in one package to provide advanced functionality.
2D, 2.5D, and 3D are packaging methods for stacking die onto other die, silicon interposers, or organic substrates. These are also done with transferring die from a wafer to another assembly to become the package. Especially with the high cost of all the elements used, the highest possible die quality is essential since rework is impractical if not impossible. Sometimes the 3D assembly is done using wafer-to-wafer (w2w) bonding which bonds entire wafers together before singulating the individual “stacks”. For w2w knowing the individual die quality of each input wafer is essential since the selection of the particular wafers to be bonded will greatly influence the yield.
Regardless of the specifics of how each of these advanced packages are configured, having KGD is required by any packaging technology that selectively moves a “good” die or combines a die with other die or components in a single package. Very few, if any, of these packaging
processes permit rework to replace a non-functioning die. Once the die is committed to the package or stack there are no fixes. Therefore, KGDs are essential to having a high yield process and avoiding potential latent defects. Without high yield, advanced packaging will not be financially sustainable to continue development let alone ramp into high-volume
Since the industry has largely ignored KGD for over a decade, it is time to revitalize the discussion. Up to the challenge? Need to learn more? Please join us for the 20 th anniversary MEPTEC KGD Workshop on December 12, 2019 at SEMI headquarters in Milpitas, California.
As always, I look forward to hearing your comments directly. Please contact me to discuss your thoughts or if I can be of any assistance.