March 14, 2013
Sunset over Phoenix, Arizona during BiTS Workshop
As the Burn-in & Test Strategies (BiTS) Workshop 2013 fades into the sunset (queue the music), here is a round-up of the highlights. There were gun fights in the corral as well as technical questions for the presenters. The saloon girls and gunfighters took an edge off of the “geek” factor. This year over three hundred fifty people come to the “Circle BiTS Ranch” (aka the Hilton in Mesa, Arizona) for the premier conference focused on what is new and next for semiconductor test tooling and strategy. Oh, did I mention that the theme this year was Western?
This was the 14th annual BiTS Workshop, which has achieved the perfect conference trifecta of Read the rest of this entry »
Leave a Comment » | 
BiTS Workshop, Cost of Test, DRAM, Interconnectology, Load Boards, Memory Technology, Moore's Law, More than Moore, My Presentations, Packaging (Semiconductor), Printed Circuit Boards (PCB), Probe Cards, Semiconductor Capital Equipment (CAPEX), Semiconductor Test, Semiconductors, Spring Pins, Test Engineers | Tagged: BiTS Workshop, Cost of Test, DRAM, Interconnectology, Load Boards, Memory Technology, Moore's Law, More than Moore, My Presentations, Packaging (Semicondcutor), Printed Circuit Boards (PCB), Probe Cards, Semiconductor Capital Equipment (CAPEX), Semiconductor Test, Semiconductors, Spring Pins, Test Engineers | 
Permalink
Posted by Ira Feldman
January 22, 2013
Intel shows first fully patterned 450 mm semiconductor wafer at SEMI ISS 2013
Attending the SEMI Industry Strategy Symposium (ISS) is like drinking from a fire hose with the additional risk of whiplash. Don’t get me wrong, it is an exquisite fire hose but sometimes the data presented can be overwhelming at this conference of semiconductor supply chain executives. The majority of the attendees and presenters are executives from the SEMI member companies that develop the equipment, materials, processes, and technology used to build, test, and package semiconductors. And the executives present from the semiconductor manufacturers are typically the “end customers”.
The greatest value of SEMI ISS, beyond the networking, is the strategic overview of the entire semiconductor ecosystem. What are the market drivers, the technology needed, and the roadmap status of this industry? It is true that we all know where we need to head courtesy of Moore’s Law and the International Technology Roadmap for Semiconductors which attempts to keep us on that trajectory. The pressure of consumers needing wanting greater functionality at lower costs is relentless. Much of the technological detail of this ecosystem is addressed in a myriad of other forums throughout the year. ISS ties these technical requirements, development needs, and business needs back to the strategic direction and desires of the global marketplace.
The whiplash comes from Read the rest of this entry »
Leave a Comment » | 2.5D/3D Stacked Integrated Circuits (ICs), 450 mm wafers, Automatic Test Equipment (ATE), Fabs, Healthcare, High Volume Manufacturing (HVM), International Technology Roadmap for Semiconductors (ITRS), Management, Market Analysis, Moore's Law, SEMI, Semiconductor Capital Equipment (CAPEX), Semiconductor Test, Semiconductors | Tagged: 2.5D/3D Stacked Integrated Circuits (ICs), 450 mm wafers, Automatic Test Equipment (ATE), Fabs, Healthcare, High Volume Manufacturing (HVM), International Technology Roadmap for Semiconductors (ITRS), Management, Market Analysis, Moore's Law, SEMI, Semiconductor Capital Equipment (CAPEX), Semiconductor Test, Semiconductors | Permalink
Posted by Ira Feldman
June 28, 2012
Click image to download presentation
Here are the highlights from Session Four “New Contactor Technologies and RF PCB Design” of the 22nd annual IEEE
Semiconductor Wafer Test Workshop (SWTW) from Monday June 11, 2012.
A last minute change to balance the schedule moved my paper “The Road to 450 mm Semiconductor Wafers” from the previous session:
Many believe that Gordon Moore in his famous 1965 paper “The Experts Look Ahead: Cramming More Components onto Integrated Circuits” that has become know as Moore’s Law, said that the number of transistors on a device would double every year (later revised to every two years). He did not say quite that. What he said was Read the rest of this entry »
Leave a Comment » | 450 mm wafers, Feldman Engineering, IEEE, Load Boards, Moore's Law, My Presentations, Photolithography, Printed Circuit Boards (PCB), Probe Cards, SEMI, Semiconductor Capital Equipment (CAPEX), Semiconductor Test, Semiconductor Wafer Test Workshop, Semiconductors, Simulation | Tagged: 450 mm wafers, Feldman Engineering, IEEE, Load Boards, Moore's Law, My Presentations, Photolithography, Printed Circuit Boards (PCB), Probe Cards, SEMI, Semiconductor Capital Equipment (CAPEX), Semiconductor Test, Semiconductor Wafer Test Workshop, Semiconductors, simulation | Permalink
Posted by Ira Feldman
June 19, 2012
This year’s IEEE Semiconductor Wafer Test Workshop started on Sunday June 10th with a pleasant surprise. Due to a welcomed but unexpected wave of seventy walk-in registrations, there was insufficient seating at the opening dinner. Thankfully the hotel staff quickly adjusted to accommodate these additional guests. Attendance and interest in this year’s workshop was clearly up.
Jerry Broz, general conference chair, welcomed everyone with a brief overview and presented prizes for the first annual golf tournament. We then quickly proceeded with business as Matt Nowak (Senior Director, Advanced Technology, Qualcomm CDMA Technologies) provided the keynote “Emerging High Density 3D Through Silicon Stacking (TSS) – What’s Next?” Mr. Nowak discussed the increased amount of hype within the 3D semiconductor packaging market in the last year with everyone announcing something. And Thru Silicon Vias (TSVs) technology has already been in high volume production for image sensors for several years now but at a significantly lower density than for 3D packaging.
Why the great interest recently in 3D packaging using TSVs today? Three simple reasons: Read the rest of this entry »
Leave a Comment » | 2.5D/3D Stacked Integrated Circuits (ICs), CMOS Imagers, Cost of Test, High Volume Manufacturing (HVM), IEEE, Mobile Devices, Moore's Law, Packaging (Semiconductor), Semiconductor Test, Semiconductor Wafer Test Workshop, Through-Silicon Vias (TSV) | Tagged: 2.5D/3D Stacked Integrated Circuits (ICs), CMOS Imagers, Cost of Test, High Volume Manufacturing (HVM), IEEE, Mobile Devices, Moore's Law, Packaging (Semicondcutor), Semiconductor Test, Semiconductor Wafer Test Workshop, Through-Silicon Vias (TSV) | Permalink
Posted by Ira Feldman
February 2, 2012
Michael Splinter (Applied Materials) - Relative industry cost improvements and volumes.
I hope that my summaries of the first day of SEMI Industry Strategy Symposium (ISS) 2012 in
provided useful insights to the economic roller coaster that is the semiconductor market and its equipment and material supply chain. There have also been several good reports Read the rest of this entry »
Leave a Comment » | 2.5D/3D Stacked Integrated Circuits (ICs), 450 mm wafers, Economics, Moore's Law, SEMI, Semiconductor Capital Equipment (CAPEX), Semiconductors | Tagged: 2.5D/3D Stacked Integrated Circuits (ICs), 450 mm wafers, Economics, Moore's Law, SEMI, Semiconductor Capital Equipment (CAPEX), Semiconductors | Permalink
Posted by Ira Feldman
January 25, 2012
After a gloomy first session focused on world economics at SEMI Industry Strategy Symposium (ISS) 2012, Session 2 – Semiconductor Markets was significantly more upbeat.
Stephen G. Newberry (Vice Chairman of the Board, Lam Research Corporation) started off with a way forward in Read the rest of this entry »
Leave a Comment » | 2.5D/3D Stacked Integrated Circuits (ICs), 450 mm wafers, Economics, Moore's Law, SEMI, Semiconductor Capital Equipment (CAPEX), Semiconductors | Tagged: 2.5D/3D Stacked Integrated Circuits (ICs), 450 mm wafers, Economics, Moore's Law, SEMI, Semiconductor Capital Equipment (CAPEX), Semiconductors | Permalink
Posted by Ira Feldman
November 28, 2011
Click image to download presentation
Back for the second year (with a minor name change), the Silicon Valley Test Workshop is an unpolished gem. Looking past the rough edges (minor logistical issues), what really shines through is the interaction of the participants. This conference really has Read the rest of this entry »
Leave a Comment » | 2.5D/3D Stacked Integrated Circuits (ICs), Automatic Test Equipment (ATE), Load Boards, Moore's Law, More than Moore, My Presentations, Packaging (Semiconductor), Printed Circuit Boards (PCB), Probe Cards, Semiconductor Test, Test Engineers, Through-Silicon Vias (TSV), ToThePoint | Tagged: 2.5D/3D Stacked Integrated Circuits (ICs), Automatic Test Equipment (ATE), Load Boards, Moore's Law, More than Moore, My Presentations, Packaging (Semicondcutor), Printed Circuit Boards (PCV), Probe Cards, Semiconductor Test, Test Engineers, Through-Silicon Vias (TSV), ToThePoint | Permalink
Posted by Ira Feldman
