Here are the highlights from Session Nine – “Productivity / COO” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 15, 2011.
Doron Avidar, Micron, “Ghosting – Touchdown Reduction Using Alternate Site Sharing“:
Even though memory testers can support very high parallelism, with smaller memories (in terms of capacity and dimensions) there are more die per wafer requiring Read the rest of this entry »
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CMOS Imagers, FLASH Memory, IEEE, Multi Layer Ceramics (MLC), My Presentations, Operations, Photolithography, Printed Circuit Boards (PCB), Probe Card Metrology Tools, Probe Cards, Product Management, Semiconductor Wafer Test Workshop, Space Transformers | Tagged: FLASH Memory, IEEE | 
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Posted by Ira Feldman
Here are the highlights from Session Eight – “RF Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 15, 2011.
Seenew Lai, MPI, “High Bandwidth (>2.5 Gbps) and Fine Pitch (< 30 µm) Cantilever Probe Card“:
The data rate of liquid crystal display (LCD) drivers are increasing to the point that traditional cantilever probe cards cannot support the required bandwidth. Using electromagnetic simulation it was determined Read the rest of this entry »
Leave a Comment » | High Frequency (RF) Testing, IEEE, Printed Circuit Boards (PCB), Probe Cards, Semiconductor Wafer Test Workshop | Tagged: IEEE | Permalink
Posted by Ira Feldman
Here are the highlights from Session Seven – “High Temp / Extreme Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 14, 2011.
Kevin Fredriksen, SPA GmbH, ”MSO – Multi-Site Optimizer”:
Most wafer probers do not supply intelligent stepping algorithms to calculate the most efficient sequence of moving the wafer relative to the probe card. (Ed: At the core of this is a traveling salesman problem.) The situation is exacerbated when Read the rest of this entry »
Leave a Comment » | DRAM, IEEE, Probe Cards, Semiconductor Wafer Test Workshop | Tagged: DRAM, IEEE | Permalink
Posted by Ira Feldman
Here are the highlights from Session Six – “Probe Potpourri” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 14, 2011.
Marc Knox, IBM, “The Development of a Flexible and Efficient Chip Thermal Imaging Capability“:
Traditional burn-in systems hold multiple printed circuit boards (PCBs) with one or more devices in burn-in sockets to provide temporary electrical interconnect to a device under test (DUT). These PCBs and sockets are known as “burn-in boards”. And the systems in which they are loaded are “ovens” that permit temperature stressing, sometimes at both hot and cold temperatures, while stimuli are supplied to the chip. The purpose of “burning-in” a device is to screen for infant mortality in an accelerated manner.
The IBM team adapted a burn-in board system to Read the rest of this entry »
Leave a Comment » | 3-D Microstructures, IEEE, Packaging (Semiconductor), Probe Cards, Semiconductor Wafer Test Workshop, Space Transformers | Tagged: IEEE | Permalink
Posted by Ira Feldman
Here are the highlights from Session Five – “Spring Pin Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 14, 2011.
Brandon Mair, Texas Instruments, “WSP-Wafer Socket Probe for Flip Chip Applications“:
Wafer socket probe (WSP) technology has demonstrated better physical and electrical performance and lower cost of ownership (COO) than traditional vertical probe cards for testing wafer level chip scale packages (WLCSP) at 0.4 mm (400 µm) pitch. These WSP probe heads are typically built Read the rest of this entry »
2 Comments | Cost of Test, IEEE, Probe Cards, Semiconductor Capital Equipment (CAPEX), Semiconductor Test, Semiconductor Wafer Test Workshop | Tagged: IEEE | Permalink
Posted by Ira Feldman
Here are the highlights from Session Four – “High Performance Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.
Bob Davis, Rudolph Technologies, “Testing Probe Cards That Contain Complex Circuitry“:
Over time, probe cards have increased in complexity from simple wire cantilever probes to those including passive components and digital control circuits. Some of these digital control circuits may even contain state based logic. At the same time the physical complexity of probe cards have increased in probe and channel counts, probe density, and total probe force. As a result, Read the rest of this entry »
Leave a Comment » | 2.5D/3D Stacked Integrated Circuits (ICs), DRAM, More than Moore, Packaging (Semiconductor), Probe Card Metrology Tools, Probe Cards, Semiconductor Test, Semiconductor Wafer Test Workshop, Through-Silicon Vias (TSV) | Tagged: DRAM | Permalink
Posted by Ira Feldman
Here are the highlights from Session Three – “Power Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.
Michael Huebner, FormFactor, “A Hot Topic: Current Carrying Capacity, Tip Melting and Arcing”:
Power consumption per dynamic random-access memory (DRAM) is increasing to as high as 400 mA or more under normal test conditions. At the same time the number of DRAMs being tested in parallel – and sharing the same power supply – is increasing. Therefore, the risk of current damage to probes is increasing.
Two distinct, but related concerns are Read the rest of this entry »
Leave a Comment » | DRAM, IEEE, Probe Card Metrology Tools, Probe Cards, Semiconductor Test, Semiconductor Wafer Test Workshop, Simulation | Tagged: DRAM, IEEE, Memory Technology | Permalink
Posted by Ira Feldman
Here are the highlights from Session Two – “Optimization / Process Analysis” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.
Steven Ortiz, Avago, “Probe to Pad Placement Error Correction for Wafer Level S-Parameter Measurements”:
Avago’s film bulk acoustic resonators (FBAR) technology usage is being expanded from filters to include oscillators. The example oscillator discussed operates at a 1.5 GHz resonant frequency with a Quality (Q) factor ranging from one thousand to several thousand and a one year aging specification of less than 25 ppm.
These devices are extremely difficult to test due to their precision and small size (not much larger than the two device pads). The drift specification is the hardest to measure. Since it is generally desirable to have at least 10x measurement capability, the drift measurement requires approximately 2.5 ppm of tester performance, i.e. 3.75 KHz accuracy at 1.5 GHz. They use Read the rest of this entry »
Leave a Comment » | High Volume Manufacturing (HVM), IEEE, Management, MEMS, Operations, Probe Cards, Quality, Semiconductor Test, Semiconductor Wafer Test Workshop, Statistical Process Control (SPC), Yield Improvement | Tagged: IEEE, Management | Permalink
Posted by Ira Feldman
Here are the highlights from Session One – “Probe Challenges” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.
Stevan Hunter, ON Semiconductor, “Use of Harsh Wafer Probing to Evaluate Various Bond Pad Structures”:
Recent product needs such as bond [pads] over active circuitry (BOAC), the use of copper (Cu) wire bonding, increased wafer probe touch downs (as many as 6 TDs), and the desire for greater device reliability has driven the need for more robust bond pads to survive wafer probing.
One method for checking for damage to the device from the probing process is via the “Cratering Test”. They etch off the top aluminum (Al) metallization layer of the pad to visually inspect for damage in the underlying titanium-nickel (TiN) barrier metal layer. If there is a problem they can spot a “crater” in the metal. They continue etching to remove the TiN layer to look for additional damage in the layer(s) below.
Leave a Comment » | IEEE, MEMS, Packaging (Semiconductor), Probe Cards, Semiconductor Test, Semiconductor Wafer Test Workshop | Tagged: IEEE | Permalink
Posted by Ira Feldman
On Sunday evening June 12th, 2011 Jerry Broz, the general conference chair, opened the IEEE Semiconductor Wafer Test Workshop welcoming us to the 21st year with a combined total attendance of over 5,000. He also briefly highlighted the positives in recent market trend data from the Semiconductor Industry Association (SIA) and VLSIresearch.
Dr. William Chen, Senior Technical Advisor, ASE Group, provided the keynote presentation “Backend to the Front Line”:
Dr. Chen started with Read the rest of this entry »
2 Comments | MEMS, Moore's Law, More than Moore, Packaging (Semiconductor), Probe Cards, Semiconductor Test, Semiconductor Wafer Test Workshop, Semiconductors | Tagged: Memory Technology, Semiconductors | Permalink
Posted by Ira Feldman
Click image to download presentation
As the final presenter at this week’s IEEE Semiconductor Wafer Test Workshop (SWTW), I outlined how critical it is to understand the true cost of a product’s architecture in “Probe Card Cost Drivers from Architecture to Zero Defects“. Without a proper understanding of these costs – especially for fully custom high technology products such as wafer test probe cards – it is impossible to maintain a sufficient gross margin. Gross margin is essential to maintain the health of a company and to fund the research & development required for innovation.
Many companies in the semiconductor test market have entered a period that Steve Newberry identified in his 2008 speech “Semiconductor Industry Trends: The Era of Profitless Prosperity?” that parallels the aluminum industry in the 1970′s. And without the means to fund innovation, companies have no future especially when faced with the double threat of Moore’s Law – increasingly harder technical requirements delivered at lower cost.
Yes, there were a few in the audience who appeared pleased since they are confident that their products are on the right path. There were others who may have been upset based upon their company’s direction. I would argue that a proper diagnosis – regardless of how disturbing – is essential to drive the proper cure.
There is plenty of opportunity in the test market and reasons for optimism. The key to long term prosperity is to really understand the fundamentals of the business and not be blinded by the technology.
I thank those who stayed for the entire conference and welcome your thoughts below. And I will be posting more about the conference (including my summaries) in the next few weeks.
2 Comments | Automatic Test Equipment (ATE), Cost of Test, DRAM, FLASH Memory, Full Wafer / 1 Touch Down Test, High Volume Manufacturing (HVM), IEEE, Market Analysis, Multi Layer Ceramics (MLC), My Presentations, Photolithography, Printed Circuit Boards (PCB), Probe Card Metrology Tools, Probe Cards, Product Management, SEMI, Semiconductor Capital Equipment (CAPEX), Semiconductor Test, Semiconductor Wafer Test Workshop, Semiconductors, Space Transformers, Test Engineers | Tagged: DRAM, FLASH Memory, IEEE, SEMI, Semiconductors | Permalink
Posted by Ira Feldman
Here are the highlights from Session 1 – Energy Generation and Storage of the recent IEEE San Francisco Bay Area Nanotechnology Council Symposium:
Dr. Dania Ghantous, V.P. Technology of Qnovo: “Lithium-Ion Batteries: Opportunities and Challenges”
Dr. Ghantous provided an overview of lithium-Ion (Li-ion) battery technology and market since Qnovo is still in “stealth mode”. She did say that battery life, charge time, and cost are Read the rest of this entry »
Leave a Comment » | Batteries, Clean Tech (Green), Electric Vehicles, Nanotechnology | Tagged: Nanotechnology | Permalink
Posted by Ira Feldman
Dr. Narayan
Here are my notes from the keynote presentation by Dr. Spike Narayan, Functional Manager IBM, “Nanotechnology: Leveraging Semiconductor Technologies to Address Global Challenges.”
He asks: can we leverage semiconductor technology to address global challenges of environment, energy, healthcare, and water? Others have made a compelling argument that Read the rest of this entry »
Leave a Comment » | Batteries, Bioscience, Clean Tech (Green), Energy, Environment, Grand Challenges, Healthcare, IEEE, Medical Devices, More than Moore, Nanotechnology, Photolithography, Water | Tagged: IEEE, Nanotechnology | Permalink
Posted by Ira Feldman
…or Memory Magic via More Than Moore
Toshiba 16 Die Stack (64 GB NAND Flash)
No this isn’t a soliloquy to an Apple iPad that is no longer, but a brief tour of the incredible memory, packaging, and system technology that can be found under the hoods of the original iPad and the iPad 2 along with some of the manufacturing and test implications. These devices clearly demonstrate the new paradigm of “More Than Moore“ where scaling of systems and packaging will propel the next wave of growth in electronics beyond the traditional doubling of performance every two years predicted by Moore’s Law. For many in semiconductor packaging and test engineering communities the issues related to More than Moore have been an academic discussion up to now, but clearly the success of the iPad product line shows the current reality for advanced devices and where the future is headed. Apple and their suppliers took huge risks in developing these new technologies in exchange for substantial returns.
As I recently noted in “Memory Alphabet Soup“, the most pressing question about memory most consumers currently have is “which iPad 2?” – 16 GB, 32 GB, or 64 GB? If Mr. Jobs believed in Read the rest of this entry »
3 Comments | Apple, FLASH Memory, Marketing, More than Moore, Product Management, Teardown / Reverse Engineering | Tagged: Apple, FLASH Memory, Memory Technology | Permalink
Posted by Ira Feldman
iSuppli Flash Market Forecast (Jan 2011)
There are so many different types of memory technologies that there is an alphabet soup of acronyms. Ever wonder why we have many different memory technologies some long forgotten with more on the horizon? I refreshed my own memory after last week’s IEEE Nano Technology Council presentation on conductive bridge random access memory (CBRAM).
The simple answer is Read the rest of this entry »
2 Comments | DRAM, FLASH Memory, Semiconductors | Tagged: DRAM, FLASH Memory, Memory Technology, Semiconductors | Permalink
Posted by Ira Feldman
