Fastest Way to Lose Customers - click for full infographic

Regardless of language or adage used, customers are the lifeblood of any business. Without customers, there is no business. How is it that businesses lose sight of this? Sometimes customers are taken for granted and are not part of a company’s core values. Other times, as organizations and processes grow in complexity they loose sight of the customer. And quite often teams don’t take sufficient time to look at themselves from the customer’s perspective.

As shown in the infographic above, it is really about the customer experience if 68% of lost customers leave due to poor treatment. It doesn’t matter whether your product or service is consumer focused (groceries, clothing, electronics, medical, legal advice, etc.) or industrial (semiconductor capital equipment, wafer test probe cards, nuclear power plants, etc.). The only difference may be the time scale and the magnitude of the relationship.

I know plenty of industrial customers who loathingly purchased products from Company X since there were no other suppliers who could meet the requirements. Company X historically was well known for its high prices and arrogance based upon their technically superior products. But I can assure you that these “customers” did everything in their power to enable the competitors. The competitors not only drove the price down, they developed more cost effective technology and have since taken significant market share. Company X is no longer the dominant supplier and their stock is now trading below their cash balance after many quarters of significant losses.

Management teams should regularly step back and take a look at their products and markets from their customer’s perspective. In addition, they should regularly audit processes and immediately make corrections especially when a customer takes the time to complain. Various statistics are reported that over half to upwards of 96% of dissatisfied customers don’t complain – they simply take their business elsewhere.

With values, it is often more illustrative to describe examples of behavior than attempt to describe the value itself.

The Good - or should I say “Excellent”?

• Nordstrom – Much has been said about their legendary service starting with the tales told in Peters and Waterman’s In Search of Excellence. I am a big fan and know from personal experience that they simply over deliver on service. Three years ago I bought a new sports coat for a very important meeting. They tailored the coat and I picked it up the day before the meeting. After my meeting, as I was getting in my car in the bright sunlight, to my horror I noticed a one inch pull near the lapel. I immediately called the menswear department to ask what I should do. The salesperson from whom I bought it was not in that day however the salesperson who answered the phone simply said it was “totally unacceptable” when I described the problem. She immediately ordered me a new coat, had it tailored and simply exchanged it, no muss – no fuss – no paperwork, a few days later.
• Apple – Regardless of the issues with their supply chain and corporate culture, their customer service is tops – both under warranty and under their paid AppleCare programs. Novice to moderate tech savvy friends swear by the “Genius Bar“. The few times I have used their support for very specific technical items, I have been impressed by simply entering your data on the Express Lane and getting a call back within the stated time (never more than five minutes). The people I have spoken to actually had considerable knowledge about the specific issue – these are not your typical call center first level employees. On occasion, they even recommended third party solutions when the Apple solution was lacking. And a big plus – the call centers were all in the US!
• Charles Schwab – We have used their financial services for several years. Every time David calls, he asks what have they put in their drinking water? They seem to understand your concerns, the first person you speak to takes ownership of your issue – no passing the buck or transferring your call, they do what they say, and they follow up. Plus they are always upbeat and pleasant. David is intimately familar with help desks having managed a back line support team for mission critical data centers and knows how hard its to have employees do this consistently well.

The Bad -

Most of us have had plenty of bad or mediocre customer service – everywhere from restaurants where the server’s smile is forced to the total chaos of the department of motor vehicles (DMV). Sometimes the employees are trapped by silly policy and procedures. Or sometimes the employees simply do not care or are otherwise indifferent to the customer’s plight. These organizations do not necessarily mean to be mediocre, they simply have not helped their staffs to understand the connection between customer satisfaction and the bottom line.

The Ugly -

This category is reserved for the worst of the worst including companies that have downright “customer abusive” policies and procedures. When you have problems with your wireless carrier, just remember their heritage and mentality of “we don’t have to. We’re the phone company.” (See Lily Tomlin’s Saturday Night Live skit for a good laugh when you are next on hold.) They are trying to improve, but they have a long way to go.

More recently, I ran in to a very abusive software company. The software products are very good – they work exceedingly well and have all the features you might want. As a customer you either pay for a monthly subscription or a slightly discounted yearly one. My yearly subscription ended in December and seeing the charge on my credit card, I decided I should drop the subscription since I was no longer using the product. I went to the website and found there is no button or form to fill out to cancel the service. It turns out you need to contact customer support. And the answer they give you is sorry, no refunds since you failed to cancel thirty days before my renewal date per their terms and conditions:

9.2 Annual Subscription by Credit Card. In the event that Your subscription to the Service is for a year and the payment is by credit card, PayPal charge or direct debit, Your subscription will automatically renew at the beginning of each subsequent anniversary year unless You or XYZ give prior written (including email) notice of non-renewal at least 30 days prior to the expiration of Your current year subscription. Upon any annual renewal, the payment arrangements in place for the prior subscription year shall remain in place, unless You and XYZ agree otherwise

This gem is buried within an eleven page, 6300 word terms and conditions page that is provided via a link when you sign up. (And when was the last time you did more than quickly skim a T&C document when purchasing software?) They don’t even provide you with an email – like many reputable firms do – that reminds you that your subscription is about to automatically renew.

The answer did not change even after escalating this to a support manager and directly emailing the president of this publicly traded company  - no refund, not even a pro-rated refund (for 11 months). A quick Google search turns out they have been pulling this sham on many people with numerous complaints to the Better Business Bureau. After indicating that I had considered buying one of their more expensive subscriptions (for web collaborating software) but would not based upon this experience, they did finally offer to “work something out”. Too late, they have just lost another customer and I am no longer recommending their software to anyone. Bottom line, I do not tolerate businesses that have policies that are simply unreasonable.

In today’s age of social media, one upset customer can have a significant audience and their complaints can influence many potential customers. An extreme example of this is David Carroll’s United Breaks Guitars video which went viral and has 11.5 million (yes, million) hits on YouTube. I’m sure that this is publicity that United would rather not have. Mr. Carroll has turned these “lemons into lemonade” and received a big boost to both his music and speaking career and helped to co-found a website for consumer complaints.

What do the Good companies know that the Bad and the Ugly haven’t figured out? It is that customers who are satisfied are better customers – they form long relationships (brand loyalty) and spend more. One survey claims that “the best customers outspend others by ratios of 16 to 1 in retailing, 13 to 1 in restaurants, 12 to 1 in airlines and 5 to 1 in hotels and motels.” And as Company X found out, dissatisfied customers will do what is necessary to become satisfied even at your company’s expense.

Therefore, you owe it to yourself to benchmark your company against the best in your industry and the world’s best companies in regards to customer satisfaction. Do you know what your customers think of your company and products? Do you proactively ask for customer inputs and are you truly listening to your customers? After looking at everything from your customer’s perspective, what should be changed? What else can be done to exceed expectations and delight your customers? In the end, success and happiness comes from happy customers.

As César Ritz, Harry Selfridge, and Marshall Field said best: the customer is always right!

Full disclosure: I’m long on Nordstrom (JWN) and am thinking of shorting the offending software company.

Michael Splinter (Applied Materials) - Relative industry cost improvements and volumes.

I hope that my summaries of the first day of SEMI Industry Strategy Symposium (ISS) 2012 in

• SEMI ISS – Snapshot of a Wild Ride – Session 1
• SEMI ISS – Snapshot of a Wild Ride – Session 2

provided useful insights to the economic roller coaster that is the semiconductor market and its equipment and material supply chain. There have also been several good reports from others at conference worth sharing:

Michael Fury at ElectroIQ has published these detailed summaries:

• ISS kicks off with IC industry reality talks
• ISS day 2: Cloud computing to drive 450mm, closer collaboration
• ISS draws to a close with innovation on the mind

Pete Singer, the ElectroIQ Editor-in-Chief, summarizes the economic overview in ISS: Top Ten Economic Trends in 2012.

SEMI has also provided a short write-up of the ISS here along with these video interviews by Debra Vogler.

Now that the reporting is finished for the informative presentations at ISS, it is critical to turn this data into actionable plans. I am busy working on strategies for my clients. How about you?

If there is something from ISS that you would like to discuss in greater detail, please let me know via email or comments below.

After a gloomy first session focused on world economics at SEMI Industry Strategy Symposium (ISS) 2012, Session 2 – Semiconductor Markets was significantly more upbeat.

Stephen G. Newberry (Vice Chairman of the Board,  Lam Research Corporation) started off with a way forward in “Profitless Prosperity Revisited: Where Do We Go from Here?”. At SEMI ISS 2008, he presented “Era of Profitless Prosperity” which compared the situation of the semiconductor integrated circuit (IC) industry to the aluminum industry in the 1970s. At that time there was sufficient demand however average price (per function or bit) was dropping significantly faster than cost (per function or bit). He identified and recommended changes that needed to occur including: memory manufacturers should restructure (consolidation and/or focus on profitability over market share), independent device manufacturers (IDMs) in the logic and microprocessor space should change their business model (become fabless, fab-light, or consolidate), wafer front end (WFE) equipment and materials suppliers should continue to innovate to continuously reduce costs of production, and collaboration across the entire supply chain should improve.

Ignoring the downturn in 2008 and 2009, demand for semiconductors has increased while average selling price (ASP) has declined and industry profitability has improved. From 2007 to 2011, semiconductor company average operating profit (OP) improved from 12% to 17% for the top 40 firms (43 in 2011). When twenty of these firms such as Intel, Taiwan Semiconductor Manufacturing Company (TSMC), fabless, and analog companies are excluded the remaining 20 companies had only an average of 1% OP in 2007 which improved to a meager 5% in 2011. Only a handful of companies dominate the profits with a lot of companies that are marginally or totally unprofitable. In fact, five of the six worst performers in 2011 with OP lower than -20% were all companies that only produced dynamic random access memory (DRAM).

Using a metric of minimum OP equal to [(capital spending (CAPEX) - depreciation + 3%)] / 75%, the companies in the fabless and mature node analog-application specific IC (ASIC) markets were stable and profitable during both 2003-2007 and 2010-2011. The microprocessor segment improved from one company (Intel) of two in 2003-2007 being healthy to all (only Intel) being healthy in 2010-2011 by Advanced Micro Devices (AMD) switching to a fabless model and being dropped from the segment. The logic IDMs are also improving by switching to a fab-light model in which they outsource fabrication of new designs at advanced process nodes while continuing to operate their own fabs for existing products.

In the foundry segment, currently only TSMC has sufficient OP to fund capital spending for advanced process nodes using cash from operations. With both GLOBALFOUNDRIES and Samsung ramping up their foundry businesses this may change in the future. In the memory market, companies producing NAND flash memory are performing while the DRAM sector is doing poorly. Additional restructuring for the DRAM space is likely ahead.

Looking at the automotive industry, Steve used a 1980 Honda Accord with a manufacturer’s suggest retail price (MSRP) of $6,155 as an example. The price of the 1980 Accord would be $17,887 today when adjusted for inflation. Not only does the 2012 Accord have substantially improved performance and many new features, it also has a much higher MSRP of $25,105. The auto industry has figured out that customers will pay more (almost 50% in this example) if the manufacturer provides more of what the customer wants or values. The increased performance and features were enabled based upon the close customer (auto company) and supplier relationship which includes the auto companies contracting their suppliers to perform R&D to provide innovation. As a result the auto-industry, even with all of its problems, has a global growth rate of 3-4%.

Moving forward, the semiconductor industry needs to similarly increase performance and value as the cost-per-function decline slows. As scaling to the next process nodes becomes more difficult, semiconductor companies will differentiate themselves by becoming the fastest to delver next-generation capability. This will require stronger collaboration with their supply chain and increasing R&D efficiency by focusing efforts on a select number of vendors. System level optimization (not just chip performance improvements from the next process node) will be necessary. In addition, there will need to be increased industry and customer-supplier collaboration to transition to 450 mm wafers in order to lower costs even faster.

Even though there were some painful adjustments (consolidation and restructuring) and there are others underway, there is a path forward to healthy companies in both the semiconductor industry and supply chain.

In “Innovation – Defining The Future of Semiconductors“, Bernard S. Meyerson (IBM Fellow VP, Innovation, IBM) started by answering the question why does IBM spend over $6 B a year in R&D? The reason is that science determines the future of technology and IBM has a long history of focusing on “innovations that matter”.

The semiconductor industry is facing many challenges including:

• The cost of developing new technology from 2004 to 2010 grew at a rate (~12.2% CAGR) faster than revenue (~ 6.5% CAGR). And the estimated cost to develop 22 nm complementary metal-oxide-semiconductor (CMOS) logic technology will be around $2.3 B – over twice the ~ $1.1 B spent to develop 32 nm.
• The rapid increase in the complexity of materials used. This can be seen in the number of elements used growing from six (H, B, O, Al, Si, and P) up to the 1990′s, adding eight more from the 1990′s to 2005. And almost all of the periodic table is in use after 2006,.
• Previously scaling was possible without significant downsides in either electrical performance or materials. Now, each reduction in feature size needs an accompanying change in materials to compensate. We are also approaching the end of scaling due to quantum mechanical effects due to the small quantity (sometimes measured in atoms) of material present.

Yes, there has been innovation to extend the current paradigm in terms of materials, 3D transistors, and system integration including 3D packaging. Beyond these, IBM has focused on what it is next – in particular non-silicon field effect transistors (FETs), 3D integration, and magnetic storage. Bernie presented IBM device research including a gate-all-around silicon (Si) nanowire transistor, sub-10 nm carbon nanotube (CNT) FET, and graphene transistors.

He also showed two 3D integration examples: one of processing multiple layers of logic, memory, and photonics on one device as it is fabricated (not assembly of multiple devices into a stack) and a collaboration with 3M to develop electronic glue that is thermally conductive to allow the stacking of more devices. IBM has determined that it is “useless to pretend they have all the skills to tackle every challenge they encounter. They need to partner and have a supplier ecosystem.” This collaboration with 3M is a good example of that partnering.

Lastly he showed very recent breakthroughs in magnetic storage using only 12 atoms per memory bit (100x the density of today’s hard disk drives) and magnetic racetracks (storage of bit patterns in each memory location).

With the “Silicon Era” of increased IT performance based upon semiconductor scaling coming to an end (in about 10 years), new approaches will be needed to drive future performance. The increased performance will come from solutions of which the IC is only a small part. For example, integration of multiple ICs at the system level and beyond including software and network functionality.

Bill McClean (President, IC Insights) in Shocks and Correlations to the Semiconductor Market examined the interdependence between various markets and the semiconductor capital market. He forecasted a 7% year-over-year growth in world-wide electronics systems which is estimated to translate to a 7% growth in semiconductors for 2012. For 2010 to 2011, even though electronic systems grew 6%, semiconductors only grew 2% so there isn’t a 1-to-1 correlation, especially as companies consume inventory. He did note that the semiconductor industry has experienced a full blown recession.

The material suppliers were not upset with flow down forecast of 7%, however the semiconductor capital companies were rather disappointed at the -16% estimated growth in 2012. (The capital equipment market did however grow 15% from 2010 to 2011.)

In terms of general trends, he did show that neither the Dow Jones Industrial Average (DJIA) nor the U.S. Purchasing Managers Index (PMI) were well correlated or leading indicators for semiconductor market. One leading indicator he does watch is TSMC who discloses their sales every month since they are on the Taiwan Stock Exchange.

What happened to their previous forecast of 10% semiconductor growth in 2011? 2011 had eleven natural disasters with an impact of over $1B which exceeded the entire decade of the 1980′s. These disasters resulted in a reduction of approximately 8% resulting in the 2% growth observed. In addition, even though DRAM is only 12% of the total IC market it sustained significant losses which substantially shifted the overall market. Whereas all other ICs except DRAM devices had an increase of average selling prices (ASPs) 2010 to 2011of 3.1%, when the DRAM losses are included the ASP for all ICs  declined 1.6%. And at the same time the overall market for non-DRAM devices grew at 5.0%, but when DRAM as added the overall market dropped 0.3% year-to-year.

In terms of the upcoming presidential election, it generally reduces the overall forecast since people can take bad news better than uncertainty. With bad news, people can make plans and move on with their lives. With uncertainty, they tend to delay action.

The semiconductor equipment forecast has steadily decreased as a percentage of overall semiconductor revenue. In 1996-2002 it was approximately 26%, from 2003-2009 it averaged 20%, and from 2010 thru 2016 it is forecasted to average around 16% as shown in the chart above. Bill also broke down semiconductor equipment spending as a function of device type and wafer volumes.

Lastly, IC Insights ranked the semiconductor companies on the basis of wafer capacity and capital spending in 2011. They identified Intel, Samsung, TSMC, Toshiba/SanDisk, Hynix, Micron, and GLOBALFOUNDRIES as the top companies with the greatest ability to compete. Bill expressed concerns about the viability of the others as these firms increase their market share.

In “Smart Grid: Overview, Issues and Opportunities“, S. Massoud Amin (Director, Technological Leadership Institute, University of Minnesota) highlights many of the challenges of the current and future power supply. By 2020, it is predicted that there will be more than 30 mega cities (cities with over 10 million people each). By 2050 this is expected to double to 60 mega cities and it is estimated that the world’s electrical supply will need to triple to keep up with demand. Over half of the US is coal powered which has been calculated to only have 1.6% overall efficiency in converting coal energy to light from generation plant to residential usage. (One major improvement to this is upgrading from incandescent light bulbs which have an overall 5% efficiency to fluorescent or LED lights with substantially greater efficiencies.)

Electronics have both contributed to energy efficiency and increased demand as greater numbers of devices are purchased and data centers are constructed. By 2030, data centers may consume 20% of the total US electricity consumed. Clearly there are challenges to be solved on both the supply and demand side.

Massoud listed the following as critical to achieve future energy demand while balancing economic and national security concerns:

• Build a stronger and smarter electrical energy infrastructure, ie. a Smart Grid
• Break our addiction to oil by transforming transportation to electric vehicles and other technology
• “Green” the electric power supply
• Increase energy efficiency

A Smart Grid would be an intelligent and resilient network that could manage peak demand, asset utilization, and reliability plus reduce emissions. Semiconductor devices would provide the brains as the grid is transitioned from an electro-mechanically controlled systems to electronically controlled one. Devices on the Smart Grid could be either controlled centrally or programmed to automatically respond to changing conditions. In order to make the extremely complex system or network that is the power grid more robust, requires a mix of intelligent devices that can act autonomously when required.

As part of their research, Massoud’s team has done extensive simulation of sensing and control strategies to optimize the network configuration and to predict how to defend the system from both attack and accidental disruption. The Smart Grid is not only an interconnected power delivery system, it is a sensor and control network where all the devices communicate. At the same time, as the grid “gets smarter”, it needs to accommodate the additional future loads especially if we wish to encourage electric vehicles.

Servicing the Smart Grid is a fairly complex market place of many different vendors supporting different components of the end-to-end network of power generation to the consumer. There is a wide range of estimates as to the global investment in Smart Grids by 2015 from $46 B (ABI Research) to $200 B with $53 B in the US alone (Pike Research). The semiconductor potential market is estimated to be $30 B alone over the next 10 years with a ~ 50% CAGR. There are substantial opportunities at all levels as the Smart Grid is designed and implemented.

James Koonmen (Senior Vice President, ASML and General Manager, Brion) presented “From Lab to Fab: Progress and Challenges for Industrialization of New Lithography Technologies“. The Internet of Things will drive future semiconductor demand. The four main end applications are media tablets, solid state drives, smart phones, and mobile personal computers (including mini-notebooks). All have greater than 15% CAGR and semiconductor revenue greater than $10 B in 2015. (Please see chart to right.)

In the last thirty years, ASML has gone from photolithography tools at 1,200 nm priced at < 0.5 M Euros / each to tools at < 18 to 32 nm priced at > 65 M Euros / each. The R&D cost of these systems has similarly increased from 50 M Euros to 1,500 M Euros. And roadmaps for logic, DRAM, and FLASH continue to call for additional process nodes at smaller and smaller features. The methods of achieving the desired sizes are immersion and extreme ultraviolet (EUV) lithography.

James provided a status update on the development progress of the NXT immersion tool. The tool is capable of 38 nm double patterning and they are working to improve it to provide quadruple patterning. At the same time, they are improving the critical dimension uniformity and production throughput. He also reviewed their “holistic” lithography product suite of tools to optimize masks prior to tape-out to maximize the process window and tools that measure the performance of the tools to control the process window. Mask optimization includes a new model based sub-resolution assist feature (MB-SRAF) and new optical proximity correction (OPC) methods.

ASML has now shipped six of the their NXE 3100 EUV systems. Four are in use by customers for development (in “production” by ASML’s definition), one is  being qualified, and one is being installed. Even though a more costly tool, the EUV systems provide single exposure patterning per layer without having to use double or quadruple patterning. This in turn has a lower total cost of ownership due to the significant reduction in processing steps, additional process equipment and additional floor space for this equipment compared to double or quadruple patterning. In the IMEC development lab, they have achieved 16 nm line / space with a single exposure using the NXE 3100.

The NXE 3300 systems are currently running at 69 wafers / hour with a resolution of 22/18 nm. As ASML continues the commercialization of the these tools over the next two years, they will reach 125 wafers / hour throughput and increase the performance of the tool. By shipping tools today to early adopters, this allows a transition plan to keep customers from over investing in double patterning equipment. Detailed status of both the NXE 3100 and 3300 development was reviewed including the development of the laser-producted plasma (LPP) and electrical discharge (DPP) sources.

Future roadmaps of how to extend EUV to less than 10 nm were shared. And ASML has plans for 450 mm wafers post-EUV transition with volume production in 2016-2018. However, this is predicated on joint industry R&D and availability of other process tools.

In “Tech Trends from the 2012 International CES“, Shawn Du Bravac (Chief Economist & Director of Research, Consumer Electronics Association) provided an overview of recent trends and what was new in this year’s Consumer Electronics Show (CES) held the week before SEMI ISS. The introduction of many new screen based products (displays, tablets, e-readers) was apparent in 2010 especially as the price of display technology went down significantly. Microsoft Kinetic was also introduced in 2010 and has since become the fastest selling consumer electronic device when it was shipped late last year.

The major themes of CES 2011 were portable vs. pocketable devices (large displays, tablets, etc.), intelligence of things (smart pill bottles, appliances, etc.), “sensor”ization of consumer devices (increasing in many devices not just cell phones), and “application” (customizing the behavior of hardware with user selectable applications). The US household on average has twenty-five consumer electronic devices and the rate of adoption is increasing.

At this year’s CES the second decade of the “digital transition” started. In the first decade, analog devices (audio devices, telephones, cameras, televisions, etc.) were converted to digital formats. In this decade we will see power of digital technology – from fully interconnected / networked devices to systems for managing the increasing digital content of our lives.

Simultaneously, computing power is being moved out of (personal) computers. In the past, it was all about how much computing power could be built in to a notebook computer. With ultrabooks it more about weight, size, battery life, or other functionality than computing power. As such, Intel was touting the sheer number of design wins for ultra books (75) over processor specifications. Google Chromebooks and tablets were also prevalent showing the rise of thin clients where the computing power is in the cloud not on the device. As the computing power is redistributed from the PC it is showing up in other devices such as televisions and smartphones.

Many new devices are built on the premise of ubiquitous network connectivity which in turn enables additional thin client applications. Several new devices were introduced either with built in connectivity (such as the Nikon D4 camera which has a built in web interface) or to connect other devices (such as personal hotspots). More natural user interfaces were also featured to make device operation easier and more intuitive. We have come full circle from the original four button television remote (limited by technology) of the 1960-70′s to too many buttons on multi-function remotes to MEMS sensor based remotes with only a handful of buttons last year to voice control (no buttons) this year.

Lastly, device use-case scenarios of many products are being defined by the end user. Original equipment manufactures (OEMs) are delivering customizable hardware and services to enable this. Everything from smartphones where the user can install applications and buy a wide range of accessories to home automation modules to vehicles remotely controlled by a smart phone and often including a video camera.

Beyond the progress in the technologies discussed in this session, all the end user markets discussed have the potential for promising growth. The day definitely ended on a high note. More summaries to follow…

Like the roller coaster ride that is the semiconductor industry, the SEMI Industry Strategy Symposium (ISS) 2012 had its share of ups, downs, twists, and turns. Semiconductor Equipment and Materials International – better known as SEMI – as the industry association of suppliers to semiconductor manufacturers has held this annual conference in early January for thirty five years to provide updates on business conditions and technology roadmaps to enable SEMI members to plan for the coming year. The conference was packed with senior management paying close attention to the industry leaders, analysts, and customer presenters. All of the presentations, even the most poorly disguised sales pitch or infomercial, contained several valuable insights.

In his keynote presentation “Technology Law Still Delivers“, William Holt (Senior Vice President; General Manager, Technology & Manufacturing Group, Intel Corporation) opened the conference with much optimism based upon the rate of transistor demand growth of 15x in 5 years (from 2005 to 2010 and again from 2010 to 2015). This growth far exceeds the reduction of cost predicted by Moore’s Law. [I calculate a 5.7x reduction = 2^(5 year period / 2 year Moore's Law cycle).] Even though there is substantial benefit by moving faster, Intel continues to scale to the next technology node every two years, simply because they can’t go any faster. And though we are closer to the limits of scaling we are not close enough to predict when it will end.  ”Perceived barriers” to scaling will be “surmounted, circumvented, or tunneled through”. Future performance improvements will come from transistor structure, materials, and integration (including new interconnects and packaging beyond current 3D under development).

The mood then turned gloomy in Session 1 - Geo-Economic Trends. Duncan Meldrum (Senior Director, Center for Forecast & Modeling, IHS) in “The Global Outlook in a Post-Financial Crisis World“ predicted slower gross domestic product (GDP) growth of 2.7% world-wide in 2012. US GDP is predicted to grow only 2% while China’s growth will slow to 7.8% and Brazil’s growth will heat up to 3.2%. This translates to a forecasted baseline of weak semiconductor consumption (measured in total wafer area) growth of 1.7% for 2012 (year over year) and 6.0% for 2103 (over 2012). All the potential risk scenarios Duncan discussed were negative, if any are partially true they would lead to even lower consumption than forecasted.

David Townes (Managing Director & Co-Founder, Needham & Company) discussed his outlook of being short term bullish and long term bearish. He reviewed data of long term trends such as the dollar having lost 99% percent of its value over the last 100 years and the average unadjusted real rate of inflation being closer to 8% than 4% as published. (Data shown in chart above.) If the real inflation rate is 8%, the real return of many investments including treasury bills (T-Bills) is negative. This chart and many of the charts presented were from Shadow Government Statistics which publishes data with the political adjustments removed. In terms of debt, he is concerned about the possibility of default leading to an accelerated debasement of the currency. He highly recommends Reinhardt & Rogoff’s book This Time is Different: Eight Centuries of Financial Folly which discusses the debt crisis. In terms of coping, at both a corporate and personal level, he suggests global diversification, holding cash of countries with net exports of raw materials (such as Canada, Australia, and Norway), keeping capital structures simple, owning real (tangible) things including equities (which is the focus of Needham’s business), and maintaining liquidity.

Lastly, in “Economic Outlook“ Robert Fry (Senior Economist, DuPont) forecasted GDP growth of 1.9% for 2012 with a possibility of higher growth in 2013 however he wouldn’t take his forecast of 3.1% seriously (yet). His leading indicators including oil prices (he prefers Louisiana Light Sweet since it more closely correlation to both gasoline prices and Brent crude from the North Sea than the oft quoted West Texas Intermediate which measures oil flowing to Oklahoma where there is a glut) points to a recession in Europe and continued slow growth in the US and elsewhere. In previous years, the semiconductor market was not correlated to general industrial production. However now that the semiconductor market has reached maturity the correlation has greatly improved with semiconductors being a slight leading indicator of general industrial production.

Robert had some good news based upon the decline in natural gas prices due to the abundance of shale rock production. This should lead to increased manufacturing in the US since most US chemicals and industrial heating uses natural gas while much of the rest of the world use oil. The lower energy costs of US natural gas should be advantageous for many industries.

His largest concerns are the risk of default in both Europe and China and US future growth. US growth is troubling since outstanding government debt is close to 100% of GDP and Reinhardt & Rogoff’s analysis shows that growth slows significantly when this ratio exceeds 90%. If an economy is growing at 4% or higher then shocks (such as defaults) can be managed. If an economy is growing at 1% or less these shocks can lead to a recession. What isn’t clear is what happens between 1% and 4% growth. The last major risk to Robert’s forecast is the quality of China’s reported economic data since he doesn’t always believe the released data and he has not found any clear leading indicators.

Following these sets of gloomy forecasts, the next session provided much needed positive news…. I will post additional summaries shortly.

Ed Pausa the primary author of PricewaterhouseCooper’s (PwC) recently published report “Continued Growth: China’s Impact on the Semiconductor Industry – 2011 Update” provided an overview at this month’s MEPTEC luncheon. His presentation was a helpful tour to start digesting this impressive report, now it its seventh annual update. The report runs 112 pages in length and is packed with figures, data and most importantly analysis. Building a cohesive picture from many disparate data sources is a major undertaking and PwC should be applauded for making available this excellent work.

After listening to this presentation and reading the report, I find two items that really stand out as primary market forces. Unraveling the convoluted web of the semiconductor supply chain to examine these items will lead to greater understanding of the industry. They are, for lack of better terms, “end consumption” and “self-sufficiency“. A semiconductor device is often manufactured in country X, then shipped to country Y for assembly into a product at which point it is “consumed”. The product then may be shipped to country Z for use by the end user (customer or business). Market data tracks a semiconductor up to the point of consumption (in country Y) whereas the “end consumption” is really in country Z. It is the market trends in country Z that flow through the entire supply chain. “Self-sufficiency” is the proportion of a country’s demand which is satisfied by it’s domestic semiconductor manufacturing.

That Asia Pacific dominates consumption of semiconductors in products (both for domestic use and export) with $160 billion of the $298 billion (2010 figures / 2011 will be similar) market total should not be a surprise to those who follow the World Semiconductor Trade Statistics. However, the graph shared by Ed (shown above, from page 11 of the PwC report) which splits the data out differently shows that Asia Pacific consumption isn’t really the Four Asian Tigers of Hong Kong, Singapore, Taiwan, and Korea. In 2010, China was 40.5% of the market (PRC not including Hong Kong) at $121 B. When China is separated out of the statistics for Asia Pacific, both the size and growth rate of the Chinese market is staggering.

Even with comparable (to same order of magnitude) gross domestic products (GDPs) of $10 trillion for China versus $14.7 trillion for the US doesn’t explain China having twice the market share for semiconductor sales as all the Americas (North, South, and Central) – 18% versus 40.5% for China. Furthermore, with a GDP per person (PPP) of $7,600 versus $47,200 for the US it is hard to believe that per person spending on products with semiconductors is on the same level and certainly not 2x. This is why understanding the supply chain to determine the point of “end consumption” is necessary. The consumption discrepancy is a result of 65% of the semiconductors used in China are either exported or assembled into products which are exported. (Graph to right from PwC page 25.)

The remaining $46.2 B of semiconductors is used to satisfy Chinese end consumption. This is significant demand when compared to $54 B of the Americas’ total demand (including semiconductors used in products domestically and exported). Unfortunately, this is where the trail of data runs cold. There are statistics about sales by company headquarter location but no readily available numbers for production or end consumption by country (other than the PwC data for China). After the presentation, Ed also indicated they were not aware of this type of data.

Using statistics from the US Census Bureau we find that the US was a net exporter of $18 B of semiconductors in 2010. And even though US semiconductor companies (based upon headquarter location) are estimated to produce half the world’s semiconductors (by value), without additional data it is hard to determine how many semiconductors are produced or end consumed in the US preventing direct comparisons with other markets such as China. Without solid data it is hard to determine which end markets really drive semiconductor demand.

In discussing overall China market growth with $108.6 B of consumption and only $21.3 B of production in 2010, Ed highlighted this $85.3 B gap. In terms of “self-sufficiency”, China can only meet 46% of its own end demand and just 20% of their total demand which enables the export of high technology products. PwC predicts these gaps will remain large (shown in the figure to the right from PwC page 94) with overall market (consumption) predicted to have compounded annual growth rate (CAGR) of 11.6% while the increase of capacity CAGR is estimated to be in the range of 10-18% depending on scenario. Both growth of consumption and production will exceed the world-wide average.

I predict that just as countries desire energy independence, China will attempt to increase its “self-sufficiency” to meet its domestic demand for semiconductors for both “end consumption” and export. It will be interesting to see how quickly they invest in production capability and technology to close this gap. With market numbers like these, China is the biggest market and will be the center of the action as they improve upgrade their technology capabilities to produce advanced semiconductors. Additional growth is likely as their PPP (GDP per capita) increases and their consumers have more to spend on electronics. Strategies that include China are essential for long term success in the semiconductor supply chain.

At this time of year, when my children see a box arrive they immediately question if it is another present for them. They are very disappointed when the Amazon.com box contains breakfast cereal or dish detergent. They are definitely thinking inside the box. If the box is large enough, they will eventually start playing in it and imagine it is not a box.

Childrens’ imagination has no bounds. Adults need to make conscious efforts to think outside the box as this can lead to innovation and creative solutions. This is often difficult due to over familiarity or lack of perspective. Two of my recent engagements illustrate the challenge:

• I was asked to evaluate alternatives, including the elimination or complete reorganization of a division, for senior executive management without engaging the existing division team. This provided an independent review of all the options, without distracting the division, enabling them to remain focused on their work.
• After determining potential future product directions, I was able to identify several software infrastructure “hooks” that could be implemented at minimal or zero cost to enable value added services. By including these hooks in new systems now and in updates for current products, the company could add new products quicker once the full strategy was determined. My outsider’s perspective and industry knowledge was essential as the existing marketing and development teams were too focused on current product challenges to plan far enough ahead.

There are many examples of creative out of the box thinking. Who would have thought the world’s largest bookseller Amazon, would also sell breakfast cereal on a discounted subscription basis? Today you may not have thought it strange when I mentioned this in the first paragraph. But I bet they would have involuntarily committed Jeff Bezos had he discussed this when he started Amazon in 1994. By constantly trying different approaches, Amazon is able to find and fine-tune profitable business models that allows them to be much more than just an on-line bookstore.

In addition to enjoyable time with friends and family, hopefully the holidays have provided you a change of routine permitting a fresh perspective and new insights.

We would like to thank all of Feldman Engineering’s clients and partners for a successful 2011. I look forward to the pleasure of working with you again this year to solve your business challenges and to think outside the box.

A happy and healthy New Years to all. May 2012 be a very successful year!

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Back for the second year (with a minor name change), the Silicon Valley Test Workshop is an unpolished gem. Looking past the rough edges (minor logistical issues), what really shines through is the interaction of the participants. This conference really has an exciting energy level missing in other forums. Beyond the greeting of old industry friends and colleagues, there was true participation and engagement. This was demonstrated in numerous ways from the dialogue between speakers and audience during the presentations to the in-depth discussions in the packed exhibit hall.

The 170 attendees were a good cross section of engineers and managers from almost all of Silicon Valley’s electronic companies. Presentations that really stood out were engineers talking about their test problems (not even “challenges”), airing their “dirty laundry” (possibly to their management’s chagrin). If you listen closely, these can be the most informative since they show real world challenges that companies are working hard to resolve.

Bill Bottoms kicked off the conference with his keynote “Test Challenges in the Era of More than Moore Technologies” providing insight into current and future test challenges. It is always exciting to see glimpses of the future based upon Bill’s work on the International Technology Roadmap for Semiconductors (ITRS). And he always has new photos of advanced technology worth knowing about.

The morning session focused on Design for Test with Al Crouch (Asset Intertech) presenting “I-JTAG Test Strategy for 3-D Chip Packages“, Steve Pateras (Mentor Graphics) presenting “DFT Trends in the More-than-Moore Era“, and Douglas Kay (Cisco Systems) presenting “Bridging the Structural/Functional Test Gap“. After lunch with considerable interaction between the attendees and exhibitors, the conference was split into two tracks: “Test Methods” and “Interface Hardware”.

Jerry Broz (International Test Solutions) started the Interface Hardware track with “Assessing CRES Performance for On-line Cleaning Optimization” an excellent review of how to systematically optimize the probe card cleaning process to balance device yield versus operational costs.

My presentation “2.5D? 3D? What? An overview of 3D IC Packaging and Test Challenges” followed. It addressed the motivation behind and the basic process flows of building stacked integrated circuits (ICs) including test implications. I also reviewed how the different organizations are addressing the challenges of developing stacked ICs along with some of the wafer probe solutions under development. Hopefully, it will serve as a good primer on the test technology issues and stimulate the discussions necessary to drive the development of production worthy solutions.

Phil Warwick (R&D Circuits) then presented “25 GB/s Socket and Loadboard Test Issues“. Phil discussed many issues that can no longer be ignored now that there has been a significant increase in the operating frequency of devices along with some unique PCB fabrication methods for addressing them. In “Pulse Current Test Considerations for Contacts“, Gert Hohenwarter (GateWave Northern) reviewed the challenges in simulating and measuring the performance of contacts when they are subjected to very high current pulses. Jim Brandes (Multitest) next presented “Kelvin Contacts – A Tutorial” discussing the basics of Kelvin measurements along with typical applications. Michael Giesler (3M) finished the track with “Impact of Embedded Capacitance on Test Socket and Test Board Performance” showing the application of 3M’s Embedded Capacitance Material which can be used for the construction of both printed circuit boards (PCBs) and test sockets.

The Test Methods track also had six papers presented. I wished I could have also attended since three of these papers were written by former Hewlett-Packard / Agilent / Verigy co-workers of mine. The papers presented were:

• “Testing a Complex USB3.0 SOC Device“, Albert Alcorn (Cypress Semiconductor)
• “Embedded DRAM: Test Challenges and Methods“, Craig Soldat (Cisco Systems)
• “Testing High Speed Memory Interface: A case for FPGA based Test Systems?”, Mathieu Duprez (MuTest)
• “Concurrent Test Method for Test Time Reduction in Production of Mobile Devices“. Amir Owzar (ST Ericson)
• “Broken Scan Chains Routinely Debugged with New Optical Technique“, Cathy Kardach (DCG Systems)
• “RF Loop Back Testing Concepts and Results“, Bob Bartlett (Verigy/Advantest)

Once again, a hearty thanks to Nick Langston for producing the Silicon Valley Test Workshop, the exhibitors for funding it, and everyone who participated! I’m definitely looking forward to next year’s event.

The MEPTEC “2.5D, 3D and Beyond – Bringing 3D Integration to Packaging Mainstream” conference was a mixed-bag. Yes, it is always exciting to hear about new suppliers and progress. But it is disconcerting to realize that the price of progress is an ongoing burden on our industry’s supply chain.

Subramanian Iyer (IBM) and Theresa Sze (Oracle) started with excellent overviews of why 3D semiconductor packaging solutions are needed to solve memory bandwidth and latency challenges to continue improving microprocessor performance. They both recognized that there are many challenges in implementing these new packaging solutions including power, thermal, and economic issues. Theresa also demonstrated why high speed optical interconnect is not be practical for multiple data channels since a single transceiver module was a significant portion of the die area and provided only 1/20 of the desired bandwidth. Phil Marcoux (ALLVIA) continued with a description of different interconnect methods and substrates that could be used to form different 2.5D and 3D configuration solutions. During a discussion of what a large die was, Dr. Iyer quipped that some IBM engineers would like to use an entire wafer for one die (which reminds me of Seymour Cray‘s early work). He went on to say they consider anything over 40 mm on a side a large die.

The outsourced assembly and test (OSAT) companies then provided updates on their assembly process technology. Marnie Mattei (Amkor Technology) provided a timeline of when they think the different kinds of chip stacking using thru-silicon vias (TSV) will be in production. Tom Strothmann (STATS ChipPAC) had a similar table of timing and end applications. Amkor currently has 40 µm pitch micro-bumps qualified for production. They are working to have 30 µm ready in the first quarter of 2012 at which time they will start 20 µm development. Marnie did say Amkor is not seeing the demand for 20 µm pitch as early as they original expected. In my opinion, anything that allows test technology an opportunity to catch up to the packaging technology is a good thing since it appears that test (once again) is lagging behind packaging development. As far as I know, there is not a production proven test solutions to contact these bumps at 40 µm pitch let alone tighter pitches.

Marnie, Tom, and Muster Wang (ASE Group) all reviewed the many variations in process flows and their companies’ silicon interposer work. All three companies noted they would take wafers with the vias formed (but prior to the wafer thinning and exposing of the vias) or the fully thinned wafers (with all the TSV processing completed). The OSATs did appear to have a preference though – for handling and yield reasons – to do the wafer thinning and finish the processing in their facility. Needless to say that both the end customer and foundry may prefer to do it the other way by sending only thinned wafers. Therefore, the OSATS say they will support both models.

Dr. Choon-Heung Lee (Amkor Technology) provided the keynote address in which he reviewed Amkor’s silicon interposer and 3D packaging technology. He also made the point more than once, with specific price data, that the technology had to fit within their customer’s cost budget regardless of the performance. A major concern is both the number of process steps and the different capital equipment required to do the wafer thinning and the micro-bump interconnect since both the process cost (number of steps) and capital equipment utilization contribute significantly to the cost of the packaging. In reviewing the technical challenges he did identify that TSV testing is a big issue but he would “leave it for another” forum or group to address starting with the Known Good Die conference to follow. Once again, the packaging and test communities did not develop this technology collaboratively and it is not clear that are they have yet fully engaged to solve the issues together.

Supply chain and back side integration challenges were addressed by Sunil Patel (GLOBALFOUNDRIES), Herb Reiter (eda2asic Consulting), and Rich Rice (ASE Group). Sunil discussed the different business models: Foundry Plus where the foundry is responsible for everything including test and assembly, OSAT Plus where the OSAT take responsibility for thinning the wafers, finishing the interconnect and any damage that may occur, and a Third Party model where an independent party owns putting all the pieces together including the memory subsystem. Herb reviewed the need for open standards to enable the entire ecosystem to enable 3D packaging along with some of the status of the groups working on these standards. Lastly, Rich reviewed some of the concerns in the supply chain starting with the $400 B gap in capital investment between the wafer fab equipment (“front end”) and assembly & test (“back end”). He also reviews some examples where the current technology may provide lower cost solutions than 3D packaging. These existing solutions may continue to be more attractive in price until the volume demand grows to fully utilize the equipment required. Therefore, careful consideration is required before switching to a new technology just because it is new especially if the performance of these solutions are not yet required.

Aveek Sarkar (Apache Design) presented some of the multi-physics challenges of power and thermal simulation of stacked die packages. He also compared simulations based upon using full die layouts (circuit based schematic) of all the dies in the stack (“concurrent simulation”) versus replacing some of the die with predictive models. The models allow simulation without disclosing the complete details (i.e. the intellectual property) of a die that may be provided by another vendor. In the two examples shown the results from each method correlated well with the other. Thermal modeling of different 2.5 and 3D packages were shown by Zeki Celik (LSI). Placing dies side by side on a silicon interposer (i.e. the 2.5D configuration) provided the best thermal performance. When the die are stacked with an interposer between them the two die reach the same temperature and the bottom die adds to the heat of the top die. The worst configuration studied is a stack without an interposer where the memory die is on top of the logic die (i.e the most common 3D configuration discussed): both die reach the same temperature which is even higher than previous example since the thermal path to the logic die is insufficient to allow the heat to escape. Nozad Karim (Amkor Technology) reviewed signal integrity modeling on 2.5D and 3D stacked packages. Key to these simulations is accurately determining the equivalent capacitance of the TSV. Due to the complexity of the system, traditional package simulation is challenging. In addition, thermal and mechanical variations will change the electrical characteristics requiring a multi physics approach for accuracy. Therefore both new tools and methodologies are needed to do this analysis.

The conference closed with a presentation by Rick Ried (STATS ChipPAC) providing an overview and “teaser” about the Known Good Die conference to follow.

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The MEMS Testing and Reliability 3rd Annual Conference gets high marks: excellent speakers focused on an emerging topic and it was large enough to have “critical mass” while allowing everyone to interact. It was well produced by MEMS Investor Journal and MEPTEC.

My presentation, “Semiconductor Wafer Test Technology and Trends: Lessons for MEMS Test Engineers“, covered the differences between testing semiconductors and microelectromechanical systems (MEMS). I reviewed the progress in test technology over the last fifty plus years, from simple cantilever probe cards to large full wafer contact probe cards, developed to reduce the cost of test.

I discussed lower cost solutions that appear counter-intuitive since they require increased technical and operational complexity. Challenges of testing MEMS devices while still on wafer (prior to packaging and singulation) were discussed along with a review of MEMS solutions at this year’s IEEE Semiconductor Wafer Test Workshop.

With the proper skills, experience, and perspective it is possible to avoid “re-inventing the wheel” and to develop the best strategy to profitably introduce new technologies to high volume manufacturing.

Here are the highlights from Session Nine – “Productivity / COO” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 15, 2011.

Doron Avidar, Micron, “Ghosting – Touchdown Reduction Using Alternate Site Sharing“:

Even though memory testers can support very high parallelism, with smaller memories (in terms of capacity and dimensions) there are more die per wafer requiring many touchdowns. For example, some of their Flash memories have upwards of 3,000 dies per 200 mm wafer. Even with a tester with 144 sites, this might require over 21 touchdowns due to resource limitations whereas some larger Flash devices can be tested as one touchdown on a 300 mm wafer.

With “ghosting”, one device under test (DUT) site on the probe card is connected in parallel to another site typically on opposite side of the probe array. This may be done for several pairs of sites. In the basic version, one of each pair of sites is in contact with a DUT while the other site is not in contact with the wafer based upon the stepping pattern. A more advanced version uses relays to switch between each site in a pair. Ghosting allows more flexibility in the shape of the probe array to improve how the probes map to the actual wafer thereby reducing the number of touchdowns required.

In the examples shown, one or more touchdowns were saved per wafer using ghosting. These reductions of 8 – 12% touchdowns translate directly to lower test time per wafer. Of course, this approach won’t help with only 1 touchdown per wafer. There needs to be approximately 4 to 20 touchdowns to gain from this approach. Even with ghosting, there may be 2 or 3 dies per wafer that cannot be tested without adding additional touchdowns. With very large die counts per wafer, it is probably more cost efficient to skip and scrap these dies. With a larger number of dies that cannot be reached, say 30, one needs to consider closely if they should be skipped or additional touchdowns added.

Since relays take up too much area on the probe card, for future designs they are looking for electronic switches that can switch all the signal & power for a die site.

Questions:

• How much complexity does this add to probe card analyzer maintenance? One needs to supply all the information for both the metrology and the floor technician. Otherwise this will fail on the tester side and the technicians won’t understand why.
• Who is the master of the test cell – tester or prober? The tester.

Larry Levy, FormFactor, “Challenges of CIS High Parallel Test“:

It surprising there hasn’t really been any detailed discussion about testing CMOS image sensors (CIS) at SWTW. Not only is there is substantial growth – driven by multiple cameras in smart phones and new automotive applications – there are also significant probe challenges.

The typical test flow has three wafer sort steps: light, dark, and logic. During the light test a calibrated light source is used to illuminate the CIS with different color light to measure response. The dark test looks at imager noise when no light is applied. Integrating light sources into the test head through the probe card present challenges. And the probe card itself needs to be designed to minimize the reflection of light and to not block the light path to the sensor array. For some applications it is necessary to embed lenses in the probe card to focus the light source.

With the growing volumes of CIS, multisite testing is required. And the shape of the test array has a significant impact on the the number of touchdowns required per wafer directly impacting the cost per unit tested. Previous multisite testing has be done with linear or diagonal arrays due to probe card limitations. With more advanced probe card technology, square arrays with skip row and skip column are possible providing significant (60 – 70%) reduction in number of touchdowns.

In addition, higher definition video with higher resolution requires higher speed CIS which in turn results in the need to move more data faster. This need for higher bandwidth requires high speed test including higher frequency probe cards. In the long term the probe card can probably carry the increasing data rate but the device may not support long rise times. Die shrinks tend to keep the die size the same since the area is dominated by the sensor. With each new process technology node, the size of each pixel is smaller. This permits increasing the number of pixels to increase the resolution of the CIS while keeping the die size the same.

In the past most CIS had bond pads on two sided pads. Current parts are moving to pads on three sides. With pads on three sides or a fourth partial side there is unopposed force from the probes so it is critical to use lower force probes to avoid pushing probes off the pads.

Noise pattern tests are sensitive to power supply levels. Placing capacitors near probes to reduce loop inductance is advantageous. As pixel size decreases there is less light collection per pixel requiring greater noise sensitivity and longer test time. With smaller pixels, greater care is needed to reduce particle generation since the particles may block one or more pixels resulting in the CIS failing the tests.

Questions:

• What is the largest size area that “pupil” lenses can be integrated into? The largest array they have built so far is 32 sites with the area inside 100 mm. Each lens is individually adjustable. However FormFactor does not have the ability to adjust the lenses, they need to be adjusted on-site on the tester.
• What percentage of parts require “pupil” lenses? It is becoming more and more common.  May not get to 70% but will be significant percentage.
• What is the pitch size of the pads? That is an interesting question. With the usage of high speed serial interfaces they had assumed there would be a reduction in the number of pads to be probed. However, it turns out that the number of pads has stayed fairly consistent or gone up slightly. There are often several pads on a tighter pitch of 100 um or slightly less. Then there are other areas of the die with larger gaps between pads.

Ira Feldman, Feldman Engineering, “Probe Card Cost Drivers from Architecture to Zero Defects“:

For a summary of my presentation please see here.

Questions:

• At our company [a semiconductor manufacturer] we have standardized our probe heads so that they are interchangeable. However as soon as you innovate you are different so how can you standardize? For actual probe technology and architecture innovation will indeed make them different. But there are many areas where we could standardize as an industry. For example the format of input data. With all the different formats used the data subject to interpreation. What does this Korean character mean over here? Others take the input form from one company and rip off the logos and email it out to other probe card companies. One person told me of a case where they misinterpreted the design file data and built the card incorrectly. They had to quickly rebuild the card at their own expense. With a standardized format the data would be unambiguous. This would allow probe card companies to build software tools to drive their metrology and design systems.
• Based upon what you’ve seen, what is one area where we should start standardization? Different companies will have pain points, therefore they will want to start in different places. As a group we should propose areas to start and solicit industry inputs to see where there is the greatest interest. It will require much work across the industry with the support of many to achieve.