Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column by mixing technology and general observations is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

Measuring Up

Tap to turn on. Wait for it to zero. Step on. I haven’t lost any weight, still 205 pounds even with all this exercise and careful eating? Step off, step back on. 212 pounds. Damn, wrong answer. Step off, step back on. 206 pounds. Okay maybe the first reading was right. Optimistically record 205 pounds. Does this nightly dance sound familiar? Not only are bathroom scales the bearer of bad news, their erratic behavior may make them one of the most despised home appliances.

I cannot say that the conversion of bathroom scales from purely mechanical systems to digital electronics has increased their accuracy. The precision of the data has increased moving from coarse analog dials to digital displays but scales do not appear to have improved accuracy or repeatability. Even though my scale displays weight to the nearest 0.1 pound (precision), the specified accuracy is only +/- 0.2 pounds. Many people, engineers included, often confuse the precision for the accuracy. (See my blog or this Wikipedia entry for a refresher on the difference between accuracy and precision.)

I haven’t done an analysis of variance (ANOVA) gauge repeatability and reproducibility (often shortened to “ANOVA gauge R&R” or simply “gauge R&R”) study of my bathroom scales and measurement techniques, but I just know the R&R is awful. Perhaps this may be a good elementary school science project for my children? In any case, it certainly is not user error… As a statistical process control (SPC) chart “junkie”, I plot each of my measurements by hand in real-time. I’m all for deep statistical analysis of data, preferably in as close to real time as possible. There is often a significant delay between when the measurement is made and when the statistics are run. By manually charting key parameters at the time of measurement, the user gains a “feel” for the data and insight into the stability of the process and measurement challenges. Beyond general optimism, I can pick the most likely “accurate” value for my weight.

The typical digital bathroom scale is based upon load cell technology where the resistance of a strain gauge changes due to the applied load. Four load cells are often connected in a Wheatstone bridge configuration whose resistance is then measured. From that resistance the strain can be calculated knowing the geometry of the strain gauge. This is certainly not terribly complex technology when compared to modern microelectromechanical systems (MEMS) based sensors. However, there are plenty of challenges in designing and producing a digital bathroom scale especially when considering the low average selling price (ASP).

Most MEMS based sensors measure fundamental forces – acceleration, rotation, and pressure – using miniature structures that move slightly. This movement results in a minute change to either capacitance or resistance that can be measured with high sensitivity electronics and used to calculate the movement. These sensors in turn provide measurements to calculate meaningful information about objects such as: How fast is an automobile moving or turning? Are the tires inflated properly? Sensor fusion adds a layer of computational intelligence to combine the data from multiple sensors in order to increase accuracy, eliminate spurious measurements, and provide greater insights into what has just happened. With my bathroom scale, I provide the “intelligence” to eliminate bad data.

For inanimate objects, MEMS sensing is fairly straightforward and accurate. But like measuring a person’s weight, measuring and providing meaningful information about people is significantly more complex. Did the wristband sensor actually measure several steps or was the user waving their arms? These measurement challenges may be why some technologists differentiate types of sensors as off-body, on-body (wearable), and in-body (implantable or digestible).

Most successful MEMS sensors to-date are off-body applications typified by automotive and smartphone applications. Even though a user may wear a smartphone, the data collected is more about the motion of the smartphone than the wearer. Not only is obtaining meaningful data easier in off-body applications, the devices may not need biocompatibility testing or medical regulatory approval.

With few exceptions, many of the mass marketed MEMS based systems today have coarse accuracy sufficient only for sensing large changes. Coarse accuracy is sufficient for idiot lights (such as low tire pressure), toys, and gadgets. I’ve noticed that my global position system (GPS) watch and sports measurement application on my smartphone (using sensor fusion of GPS and MEMS sensors combined with map data) are always slightly “off” in terms of distance for my bicycle rides. And neither measures exactly the same as my wheel based odometer.

The distance difference on these devices is minor compared to the ~2x difference in vertical climbing and ~3x difference between calculated calories. I could probably design a gauge R&R study and calibration method between the devices for distances, possibly for vertical climbing, but what about the calorie difference? As much as I am interested in improving my physical performance, perhaps I am better off enjoying my bike ride and the half-gallon of ice cream that the high calorie expenditure data permits. As the demand for self-awareness and quantification devices such as activity monitors and calorie counters grows, a greater number of enthusiasts are likely to push for increased accuracy. As MEMS sensor technology improves, market-leading product companies will find it easier to supply high accuracy and repeatable devices at reasonable costs. I look forward to the day when all of my devices have a much higher degree of correlation to each other.

As applications move to on-body or in-body their sophistication, accuracy, repeatability, and reliability need to increase significantly. This will permit many of the devices that are currently closer to toys and gadgets to become better diagnostic tools. The desire for self-administered medical diagnostics, often envisioned using a smartphone as the computing and connectivity engine, comes with significant system performance challenges. These devices may start out as “idiot lights” for our body – i.e. time to see the doctor for “check engine” – but greater specificity to provide “medical grade” measurements will be demanded over time. System accuracy and repeatability will be essential to detect acute symptoms and prevent false positives.

Once medical or mission critical reliability is proven for more than a handful of devices, MEMS will quickly move from on-body to in-body applications. At the same time MEMS has the opportunity to move from measurement to interaction. The unique size of MEMS may enable multiple measurement points and/or new therapeutic methods. High volume MEMS fabrication processes and packaging technologies that lower costs will increase the adoption rate of home or individual centric point-of-care. This greater access to advanced automated healthcare in non-clinical settings should reduce out-of-control medical spending.

Properly measuring, analyzing, and adjusting human activity and medical state are clearly challenging tasks. As a MEPTEC committee member, I’m looking forward to the upcoming conference “MEMS-enabled eHealth Revolution” focusing on sensors, actuators, and architectures that enable advanced healthcare applications. One particular interesting area is how biological sensors and actuators may differ greatly from “traditional” MEMS due to unique requirements of these “wetware” devices.

If your curiosity includes how to make these devices work better than your bathroom scale, I look forward to seeing you at the conference!

Let us continue the discussion below. I welcome your comments!

Sunset over Phoenix, Arizona during BiTS Workshop

As the Burn-in & Test Strategies (BiTS) Workshop 2013 fades into the sunset (queue the music), here is a round-up of the highlights. There were gun fights in the corral as well as technical questions for the presenters. The saloon girls and gunfighters took an edge off of the “geek” factor. This year over three hundred fifty people come to the “Circle BiTS Ranch” (aka the Hilton in Mesa, Arizona) for the premier conference focused on what is new and next for semiconductor test tooling and strategy. Oh, did I mention that the theme this year was Western?

This was the 14th annual BiTS Workshop, which has achieved the perfect conference trifecta of content, engagement, and environment. Once again, the weather was fantastic even for those of us from milder climates: sunny and warm 70-80 F during the day. The Hilton pulls out all of the stops for this conference with a great facility and darn-tasty vittles. The weather and hotel merge to form the foundation of the great environment. It is no wonder why BiTS keeps returning to this particular “ranch” every March. And many attendees are repeat participants.

But the real cornerstones of the event are the technical conference and the expo. Having been roped-in to join the committee, I quickly learned of all the hard work that goes into getting the right content. My ten gallon hat is off to the other committee members for wrangling their technical sessions. Over the years, the committee has done an amazing job expanding the horizons of this conference from “just” sockets for test and burn-in into all of the “tooling” (load boards, fixturing, thermal management, cabling, and yes even some probe cards) required for testing semiconductors.

I had the pleasure of wrangling Session 6 “And, at the Wafer Level” which addressed the challenges of performing final test and burn-in at the wafer-level. As the deployment of wafer level chip-scale packaging (WLCSP) increases, many users have adopted or investigated the use of spring-pin based wafer probe cards for final test. Jim Brandes (Multitest) in “Spring Probes and Probe Cards for Wafer-Level Test” and James Migliaccio (RF Micro Devices) in “A Comparison of Probe Solutions For an RF WLCSP Product” covered this topic well. Steve Steps (Aehr Test Systems) discussed many of the issues that drive the need for wafer-level burn-in in “Wafer-Level Burn-in Decision Factors”. In “Bridging Between 3D and 3D TSV Stacking Technologies”, Belgacem Haba (Invensas) described new technology to increase the performance of multiple stacked dynamic random access memories (DRAM) in one package and package-on-package (PoP) applications. Invensas’ Dual Face Down (DFD), Quad Face Down (QFD), and Bond Via Array (BVA) technologies should help to fill the product roadmap gaps between existing solutions and true 3D packaging which is not expected to be widely available sooner than 2016. Mr. Haba was awarded the “Most Inspirational” presentation. Once again, I would like to thank all of the presenters, especially those in my session, for their hard work.

There wasn’t any hog-calling or yodeling on the Talking Points panel hosted by Françoise von Trapp (Queen of 3D, Impress Labs). It was my pleasure to join Scott Jewler (Advanced Nanotechnology Solutions), Chris Scanlan (Deca Technologies), and Sitaram Arkalgud (Invensas) to discuss “Interconnectology: Inspiring a Paradigm Shift”. As Dennard Scaling, which has been the main engine allowing the semiconductor industry to keep up with Moore’s Law, may be coming to an end and the price per transistor is no longer dropping there is a need for More than Moore solutions. Interconnectology is the development of new interconnect technologies – at the integrated circuit (IC) package, printed circuit board (PCB), and system level – to enable new or improved performance at lower overall product cost. Take a look at Françoise’s write-up about the panel and keynote by Bill McClean (IC Insights) for additional insights into Interconnectology. And feel free to add your comments below on your thoughts of adding Interconnectology to the lexicon.

The expo had a vast array of exhibitors from various parts of the test supply chain. From starting material (plastics, ceramics, and high performance alloys) to interconnect elements (spring pins, elastomers, PCBs, cables, etc.) to capital equipment (burn-in environmental systems, packaged part handlers, etc.). There were services companies, system integrators, and custom solution providers. All of the exhibitors were focused semiconductor test and the electrical, thermal, and mechanical solutions required to provide the interconnect from the device under test (DUT) to the test system. The expo is a very popular component of the workshop as it provides the opportunity to find solutions for one’s test challenges and to see the latest developments. And maintaing a focus on test keeps it from becoming overwhelming unlike the much larger expos which try to have something for everyone. From the comments I heard, everyone always enjoys the one-on-one engagement and networking opportunities the expo provides. It is no wonder that the expo sold out (again) and a secondary ballroom was added to accommodate everyone who wanted to exhibit.

The BiTS Workshop is an enjoyable and worthwhile event if you are involved in test due to the excellent content and networking. It is extremely valuable to understand the test technology challenges and appropriate test solutions. And we certainly have a bit of fun along the way. So as we hit the trails to tackle our technology challenges, I look forward to crossing paths soon. If I can ride shotgun and help you out partner, don’t hesitate to holler!

Intel shows first fully patterned 450 mm semiconductor wafer at SEMI ISS 2013

Attending the SEMI Industry Strategy Symposium (ISS) is like drinking from a fire hose with the additional risk of whiplash. Don’t get me wrong, it is an exquisite fire hose but sometimes the data presented can be overwhelming at this conference of semiconductor supply chain executives. The majority of the attendees and presenters are executives from the SEMI member companies that develop the equipment, materials, processes, and technology used to build, test, and package semiconductors. And the executives present from the semiconductor manufacturers are typically the “end customers”.

The greatest value of SEMI ISS, beyond the networking, is the strategic overview of the entire semiconductor ecosystem. What are the market drivers, the technology needed, and the roadmap status of this industry? It is true that we all know where we need to head courtesy of Moore’s Law and the International Technology Roadmap for Semiconductors which attempts to keep us on that trajectory. The pressure of consumers needing wanting greater functionality at lower costs is relentless. Much of the technological detail of this ecosystem is addressed in a myriad of other forums throughout the year. ISS ties these technical requirements, development needs, and business needs back to the strategic direction and desires of the global marketplace.

The whiplash comes from the sense of scale and the range of numbers presented. Talking about 10 nm process technology on 450 mm wafers is almost 10 orders of magnitude. Robert Bruck‘s (Intel) “one more thing” was to show one of the first fully patterned 450 mm wafers that Intel will loan to equipment companies for tool development.

The market numbers are even more astounding. According to Bill McClean (IC Insights) ihe average selling price of an integrated circuit (IC) was $1.35 with an astounding 193 billion (yes, billion with a “B”) units shipped in 2012. This $259 billion global semiconductor market needs to be viewed in the context of an estimated $60 trillion in global gross domestic product (GDP) for 2012. From 2010 through 2012, McClean found a 0.99 correlation between GDP growth and IC market growth which he predicts will continue through 2016. Therefore, thinking about the monetary scale requires twelve (12!) orders of magnitude. Definitely, difficult to quickly wrap one’s thinking around. The global markets may be why ISS opened with three economists starting with a keynote by John Williams, President and Chief Executive Officer (CEO) of the Federal Reserve Bank of San Francisco on Monday. When was the last time you needed to include quantitative easing in the market analysis of your technology product?

From the global economic outlook and semiconductor market forecasts, the conference shifted to exploring the drivers of these markets in the second half of Monday. Tuesday morning was focused on discussion of supply chains for end customers, equipment manufacturers, and material suppliers. During Tuesday afternoon, strategic development in materials were discussed. Jan Vardaman (TechSearch International) delivered a well needed wake up call that 3D semiconductor packaging is simply not ready for high volume manufacturing (HVM) on the basis of material availability, process readiness, and enabling electronic design automation (EDA) tools.

Wednesday morning started with the “Opportunities at the Edge” exploring the future direction of technology applications including cognitive systems by Dario Gil (IBM), utility scale solar power by Peter Carrato (Bechtel Corporation), advances in automotive technology by Kal Gyimesi (IBM), and ingestible ICs used to uniquely identify medicine a patient swallows by Andrew Thompson (Proteus Digital Health). The final session of the conference was the “Streetviews Panel” where financial analysts provided their insights into the semiconductor equipment and materials market.

Each session and every presentation was excellent and worthy of a detailed summary. What is critical is knowing how the information presented impacts a specific market segment. The equipment and materials market along with the supporting markets of semiconductor and automated test are too large to be treated homogeneously. I am certain that every executive present at ISS was busy filtering the data through the lens of their business and specific markets. Without this focus it is difficult to absorb everything covered, similar to the challenge of scale with 9 to 12 orders of magnitude. Throughout the coming year, what I have learned at ISS will help me shape the big picture and provide critical knowledge for detailed analyses when working to solve my client’s problems.

I may also explore one or more of these gems of knowledge in more detail in a future blog post. I am certain know this knowledge will serve me well until ISS next year. In the meantime, if you would like to discuss how any of this relates to your business challenges please don’t hesitate to ask me.

As we bid adieu to 2012, I realize that I have been remiss in providing updates on all of the exciting activity since my last one in May. I will rectify this situation below and have added regular updates to my list of New Year’s resolutions.

Challenges

In May, it was great to see the many responses to the Big Hairy Audacious Goal where Janusz Bryzek (Fairchild Semiconductor) challenged the microelectromechanical systems (MEMS) industry at the MEMS Technology Symposium that I described in “Thinking Big: $1 Trillion MEMS Market” (part 1 and part 2). 

In June, I reviewed the test challenges of the transition to 450 mm semiconductor wafers with my presentation “The Road to 450 mm Semiconductor Wafers” at the IEEE Semiconductor Wafer Test Workshop (SWTW). I have posted summaries of this entire excellent workshop: keynote and sessions 1, 2, 3, 4, 5, 6, 7, 8, and 9.

In one very hectic July week, I attended the summer working meeting of the International Technology Roadmap for Semiconductors (ITRS), the SEMICON West trade show, and the Test Vision 2020 conference. The focus of ITRS is to determine the technology path forward to coordinate the entire semiconductor industry. This roadmap guides the development of new technologies to improve performance and lower the cost of electronics. While ITRS looks ahead, companies at SEMICON display and promote their equipment and technology developed in accordance to the roadmap to continue the industry’s progress. Lastly, Test Vision presentations look at recent advances and near term futures of semiconductor testing. The testing challenges of 3D semiconductor packaging, an area that I am very focused on, was one of the hot topics at all three events.

Closer to home in August was the Silicon Valley Test Workshop where I was honored to chair the afternoon presentations. The MEMS Testing and Reliability conference in October examined in depth the challenges of testing MEMS. My session summaries can be found here: 1, 2, 3, and 4. In November it was my pleasure to be on the panel discussing “The 3D Buzz: Hype versus Reality” at the IEEE International Workshop on “Testing Three-Dimensional Stacked Integrated Circuits“. My fellow panelists and I have moderator Françoise von Trapp (Impress Labs) to thank for our starring roles in this humorous winter video.

In December, the RTI International 3-D Architectures for Semiconductor Integration and Packaging conference closed out this very busy year with my summary for Chip Scale Review.

Solutions

During the last six months, I completed several exciting consulting projects including:

• Comprehensive market study of suppliers, including taxonomy of technology, for precision interconnect.
• Supply chain analysis for mobile electronics including multi-user web database.
• Due diligence for a merger & acquisition (M&A) transaction including extensive customer interviews .
• Product development Life Cycles for multiple companies.
• In-depth company and technology briefings.
• Market analysis for multi-year strategic planning including technology trends.
• Identification and screening of overseas representatives.
• Press releases and publicity.

If you would like to discuss any of these in greater detail or how a similar project might relate to your needs, please let me know.

I also started my Coupling & Crosstalk column in the MEPTEC Report with “Painting Lessons” and “Quality for the Long Haul?“. I hope these columns mixing technology and general observations are thought provoking and “couples” with your thinking. Do let me know your thoughts via the comment sections.

Future

One of the first events on my 2013 calendar is the SEMI Industry Strategy Symposium January 13-16 in Half Moon Bay, CA. I look forward to seeing many of you, along with other industry executives, to discuss the direction of the semiconductor industry and the economy in general.

More on my calendar will be included in my next update.

Please do not hesitate to contact me if Feldman Engineering can be of any assistance.

I wish you and your family good health and great prosperity in 2013!

Ira

Feldman Engineering develops and markets unique high technology solutions and business strategies. We assist companies in the semiconductor, nanotechnology, and MEMS industries move products from concept to customers.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column by mixing technology and general observations is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

Quality for the Long Haul?

Does a manufacturer’s responsibility and interest in quality end when the warranty expires?

When is death premature? People have life expectations based upon family and societal statistics as well as their health. Mechanical devices, especially those with moving parts, have estimated lives and known wear out mechanisms. Cars currently have an average age of 11 to 13 years of useful life which allows consumers to set reasonable expectations of service life. What about electronics? What is a reasonable expectation of service life?

I had a few devices at home fail recently which makes me wonder about the reliability of consumer electronics. Have quality standards fallen and have we reached the point of truly disposable electronics?

The Weakest Link?

A four-year-old LCD computer monitor intermittently failed to turn on. A quick Internet search found several others with this same monitor who also had the exact issue. (Google is a fantastic diagnostic tool: query the make, model number, and a description of the symptom and you are likely to find others victims of the same issue plus often a solution.) People reported fixing the problem by replacing faulty surface mount chip capacitors on the motherboard. Since the monitor was no longer under warranty, the cost to have someone diagnose let alone repair this problem far exceeded the cost of replacing it.

My father in-law’s rarely used six-year-old DVD player died mid-movie, disappointing everyone. A Google search identified a capacitor (C318 in the power supply subsystem) as the most likely culprit. With new DVD players costing less than $50, I wasn’t too interested in confirming root cause failure. However, I did have to disassemble the player to retrieve the disc stuck inside. Clearly a system design failure since the unit did not fail in a safe or convenient mode. Upon opening the unit, it was clear that C318 was indeed blown.

My very small, and likely statistically insignificant, sample of failed devices appeared to indicate a trend. Do capacitors have a higher failure rate than other more complex electronic parts? Capacitors, if the circuit is designed and manufactured correctly, should have an extremely low failure rate. Some models predict the life of a capacitor increases by the square of the difference of the maximum rated temperature minus operating temperature. By selecting capacitors with a higher temperature rating, this can easily increase the expected life. Regardless of operating a capacitor well below its maximum specification to extend its life, many formulas limit the useful life of an electrolytic capacitor to 15 years due to material aging. If more of our electronics lasted 10 to 15 years, I doubt anyone would say they failed prematurely since their functionality would likely be obsolete by that time.

Why the premature failure of capacitors in these products? Did you know there is a global epidemic of capacitors failures that started in 1999 named the “Capacitor Plague”. (Go ahead, Google it – I’ll wait.) This has led to a rash of class action lawsuits with major electronics manufacturers going on the defensive. Some trace these failures to improperly manufactured capacitors from Taiwanese suppliers that undercut the price of previously dominant Japanese suppliers. As interesting as the claims of industrial espionage and theft of technology with the resulting lawsuits are, I doubt they will be the basis of the next John Grisham novel.

Quality Failure?

Though these particular failures may have a root cause of improper component design and manufacture, I believe the Capacitor Plague is indicative of fundamental failures in product quality as a result of the dis-integration of the global supply chain. Even worse are some brands whose sole involvement in the product is the receipt of a royalty check. I’ve had several cordless telephones branded “AT&T” and “RCA” that were designed and manufactured by third parties with little to no involvement from these formerly pioneering electronics companies. In fact, “RCA” is simply a trademark licensed by RCA Trademark Management to others who actually build and sell electronic products.

For some companies, the only quality concern appears to be whether they can get through the ever-shrinking warranty period without a rash of expensive returns. Formerly, most vertically integrated companies did an analysis between engineering, manufacturing, and quality organizations to determine the required quality and reliability levels. The objective in setting these levels was achieving a field failure rate below a given limit that supported the product’s financial (warranty) objectives. These levels translated into reliability goals, test and qualification plans, and vendor management plans for each component in the system. With the increased use of outsourced manufacturing, fragmented supply chains, and higher levels of sub-system integration, accurate quality level planning has become exceedingly difficult if not impossible to achieve.

Extended warranty plans have become profit centers for consumer products. Only a few plans are offered by manufacturers themselves, so there is little incentive to improve product quality. Most plans are sold by retailers at a substantial profit and underwritten by insurance companies. Therefore, there is little pressure for retailers to push manufacturers for longer warranties. Doesn’t it seem odd that most smartphones come with a hardware warranty (typically one year) less than the length of the wireless carrier contract obligation (typically two years) required for the promotional price? Most wireless carriers aggressively market an extended warranty plan instead of working to increase the hardware warranty.

Capital equipment companies, including commercial computing and networking companies, do track their field failures since much of their equipment is on a support contract after the initial warranty period. These failures directly impact the equipment company’s bottom line, so they keep careful track both to improve new designs and to set support pricing for older equipment. Rather direct feedback on quality is received when a prospective customer calculates total cost of ownership including quoted support costs.

Consumer brands, excluding perhaps products such as cars with long warranties and service plans paid for by the manufacturer, have much smaller direct incentives to manage their post warranty failure rates. Marketing should join the conversation with engineering, manufacturing, and quality to set appropriate quality goals. Yes, the product might survive the warranty period but if it dies prematurely, before the customer is ready to move on, the brand will become synonymous with junk.

Let us continue the discussion below. I welcome your comments!

Lego Blocks (flickr: antpaniagua)

My event summary recently published in Chip Scale Review Tech Monthly:

Is 3D semiconductor packaging really the Lego of the integrated circuit (IC) world? It is a great analogy for the range of possible solutions and flexibility provided by different flavors of 3D packaging (2.5D on interposer, 3D, 5.5D, etc.) and “colors” (homogenous and heterogeneous) of die stacks. Plenty of pictures of Legos and scanning electron microscope (SEM) images were shown last week at the RTI International Technology Venture Forum symposium and conference “3-D Architectures for Semiconductor Integration and Packaging”. Presenters clearly articulated the great promise of what could be built with 3D packaging. At the same time, progress towards solving the multitude of challenges to make this technology as pervasive, if not as easy to use and fun, as Legos was discussed.

The challenges span …

Please click to continue reading on the Chip Scale Review website.

Can reliability and production testing keep pace with the explosive growth in  microelectromechanical system (MEMS) based product volumes? Soon it will be the rare consumer product that does not include a MEMS device bringing us closer to the possibility of a $1 trillion MEMS market. In order to achieve greater adoption of the technology, cost and quality goals will need to be met through testing and reliability. This was the focus of the MEMS Testing and Reliability 2012 conference produced by MEMS Journal and MicroElectronics Packaging and Test Council (MEPTEC).

Session 4

Mervi Paulasto-Kröckel (Professor, Aalto University) in “On the Reliability Characterization of MEMS Devices” examined the current methods for reliability assessment in MEMS devices and identified necessary improvements. Currently, the reliability of MEMS devices are evaluated in the functioning state. A sensor is tested by applying a known stimulus and comparing the sensor output while varying the test conditions such as temperature, humidity, etc. MEMS actuators are similarly tested by providing a known input and measuring the output of the actuator over the range of test conditions. Significant deviation between the expected and measured result indicates a failure. Simple functional test is appropriate for manufacturing quality testing however it is inadequate for measuring and improving device reliability.

Professor Paulasto-Kröckel compared these processes commonly used to estimate MEMS reliability to those used in the microelectronics industry. She identified major methodology changes required in MEMS testing based upon the extensive experience of the microelectronics industry. Today’s reliability testing can be considered a three step circular process: Design of Experiment (DOE), Functionality Test, and Observation. The Observation step is where the engineer analyzes the data to see what happened during the test. The engineer then suggests changes to the design which if needed requires a new cycle starting with the DOE to confirm the changes. This is clearly a trial and error based method typically leading to long delays due to the design and manufacturing process required before additional tests can be performed. Testing the device simply as a black box does not lend itself to the understanding of the physics of the failures to improve future designs.

The microelectronics industry has adopted a more robust method for reliability testing which uses a four step circular process: DOE, Reliability Test, Failure Analysis (FA), and Device Modeling. There are two significant differences from the methodology currently used for MEMS. First, reliability testing is designed to stress the device based upon known or predicted failure modes not to simply test the device over a wide range of test conditions. And secondly, the failure analysis goes beyond the functional test results to determine the fundamental physics of why the failure occurred. This data is then used to update the device models used to predict the behavior of the device based upon the fundamental physics. The models are then used to predict how the changes will improve the device and to start another cycle of reliability testing.

MEMS devices should be tested through a similar four step process. Unlike electronics which do not move, MEMS devices are more complex in terms of the fundamental physics and physical properties. This makes the modeling more challenging since energetics and kinetics need to be clearly understood and how they impact the microstructures of the device during operation. For example, a stress-strain analysis needs to be performed to make sure that the limits of the material and design are not exceeded within the specified operation range of the MEMS device.

Examples of applying this four step methodology to a MEMS gyroscope and microphone were reviewed in depth by Professor Paulasto-Kröckel. Even though the test conditions were different, the same process was used in both cases. The gyroscopes were tested for shock impact and surprisingly the electronics failed sooner than the package itself at roughly half the force. FA and modeling were done to understand the failure of the electronics, package, and MEMS structure. The MEMS failure modes predicted by the models were confirmed by microscopy. Shock testing on the microphones confirmed two failure modes suspected in the design by the initial finite element analysis (FEA) modeling. These results show the value of this four step methodology and includes a better understanding of the physics of the failures.

High temperature and humidity testing was also performed on both devices. Lastly, corrosion tests were performed on the microphones. The team is currently analyzing these results and will work to update the models to better understand the physical basis of potential failures under these conditions.

In “Dynamic Product Performance Testing of Capacitive MEMS Elements at Wafer Level”, Hugh Miller (Founder, Chairman and CEO of Solidus Technologies) reviewed how MEMS devices can be dynamically tested on wafer using only electrical stimuli. The Solidus system performs this dynamic test by electrostatically activating the MEMS structure, applying a drive voltage and measuring the system response. Typical sensors, unlike actuators, are not designed to be electrostatically actuated. However, it is often possible to excite the sensor structure using a voltage to drive the sense elements (often a comb structure whose movement is designed to be sensed by the change in capacitance) electrostatically. The voltage levels required to initiate movement may be significantly different from those used to measure the capacitance. Therefore, these voltages are best applied by the test system rather than the electronics packaged in the MEMS device.

There are several different tests that can be applied in this manner. The first is applying the drive voltage as a pulse and then measuring the output (typically the capacitance) to determine the step response of the particular unit. Like a typical damped oscillator, most MEMS devices will resonate from the initial pulse and the signal will decay over time. The resonant frequency, Q, and damping ratio can all be calculated. A variation in any of these factors from baseline would indicate a difference in the particular device due to a defect or manufacturing variation. These factors can also be correlated to final package or system performance thereby eliminating bad devices earlier in the manufacturing process. By performing this test at the wafer level, the cost of packaging and testing a bad device can be avoided. The fact that a MEMS device often has an integrated application specific integrated circuit (ASIC) inside the package makes it even more important to eliminate bad MEMS devices before packaging to lower costs and avoid wasting good ASICs. 

Other waveforms can be used to perform tests in a similar fashion. A signal that ramps up and then down can be used to test the range of motion of the element, to determine if there is no stiction, and to measure the hysteresis of the device. A sweep frequency waveform can also be used to determine the resonant frequency of the part. As with the step response, using these and other tests the response of the particular unit can be compared to the baseline to identify unit to unit variation and potential defects. The baseline is determined either through modeling and/or characterization of reference parts. By performing these tests at wafer before packaging, not only will there be cost savings but quicker feedback if process or design adjustments are required.

Can reliability and production testing keep pace with the explosive growth in  microelectromechanical system (MEMS) based product volumes? Soon it will be the rare consumer product that does not include a MEMS device bringing us closer to the possibility of a $1 trillion MEMS market. In order to achieve greater adoption of the technology, cost and quality goals will need to be met through testing and reliability. This was the focus of the MEMS Testing and Reliability 2012 conference produced by MEMS Journal and MicroElectronics Packaging and Test Council (MEPTEC).

Session 3

Pavan Gupta (Vice President of Operations, SiTime) provided a cautionary tale in “Packaging and Reliability Qualification of MEMS Resonator Devices”. Historically many MEMS companies have failed to start the device and package co-design as early as possible even though packaging was upwards of 80% of the product cost. [Perhaps they aren't really using a concurrent engineering methodology?] Even though the cost of packaging has dropped significantly, the complexities and risks related to packaging remain high.

There are many challenges related to MEMS packaging since without a reliable and qualified package, it is not possible for one’s customers to easily and confidently integrate a MEMS product into their end product. In SiTime’s case they had a double challenge of having to qualify their new technology while meeting or exceeding the customer’s expectations of a typical quartz oscillator. Quartz oscillators are a well established technology with specific qualification procedures to ensure long-term reliability. For example, there are JEDEC and US Military Standard (MIL-SPEC) quality standards that define precise test procedures to qualify quartz oscillators. These test procedures however are based upon both the end application and the technology being tested (quartz oscillators). These standards are designed to stress and push the technology, sometimes to failure, often based upon known failure modes and technology sensitivities. The challenge is to not only pass the reliability tests for the technology being displaced but to demonstrate reliability based upon the end application and sensitivities of the new technology.

Even though there were several existing MEMS packaging technologies available to SiTime at the start of their development, these were inappropriate for their product. For example, typically MEMS packaging at 1.4 mm was too tall since the mobile electronics industry is moving to less than 1 mm. Some of the packaging developed for sensing often contain a hole to expose the MEMS element to the environment which might be a problem for the device. Making any change, regardless of how minor it appeared, to the existing packaging and processes requires a full validation and qualification effort. These efforts frequently take significant time and money, two things that are in short supply for a startup such as SiTime.

In order to accelerate customer adoption, SiTime decided to use existing quad-flat no-leads (QFN) packaging to mimic the form factor of existing quartz oscillator packaging. From an assembly process development perspective, this was a good choice since there were no MEMS-specific changes required. They quickly ran into the issue that quartz oscillator packages are typically hermetically sealed providing a moisture sensitivity level (MSL) of 1 (at 260 C). An MSL 1 rating means the package will survive the assembly process regardless of how long it is exposed to moisture prior to being soldered to the printed circuit board (PCB). Any other MSL rating requires expensive special shipping containers and/or limits the shelf life of the parts. Therefore, to be drop-in equivalent they needed to achieve this rating which took them three iterations of packaging process each taking two to three months to complete. After validating the “final” process they had to complete a full qualification which took three months. All told, this one qualification aspect took the better part of a year to complete.

Mr. Gupta then reviewed the effort to construct a good qualification plan. First, they started with various product requirements and standards across several technology areas including quartz oscillators, MEMS devices, and QFN packaging. They selected test procedures that would predict the failure rate over time, failure modes, and failure mechanisms. Then they had to engage with their target customers to review this plan. Beyond the industry standard tests, many customers have specific additional tests they want run based upon their end product requirements, areas of concern, and areas they have seen failures in before. The process of defining the qualification plan takes a fair amount of time and effort but is important to have defined prior to starting the tests, some of which can take many months.

SiTime performed a high temperature operating life (HTOL) test, common for semiconductors that use both temperature and voltage stresses, to perform accelerating life testing to predict the life of a device. Devices are placed in a burn-in oven to heat and apply voltage to stress the parts. The parts are then removed at various test intervals (168, 500, 1000 hours, etc.) and electrically tested to checked for failure. (A basic burn-in setup does not perform testing during the burn-in time whereas some more advanced burn-in ovens may enable this.)

In addition, to the HTOL testing, which is very appropriate for SiTime’s device since it contains an application specific integrated circuit (ASIC) to control and read the MEMS element, SiTime’s customers required a dynamic aging test. This test takes a quantity of the devices at a specific temperature and measures the operation of each device over an extended period of time to make sure there is no change. For this particular product, SiTime had to construct two custom test setups, one at 25 C and one at 80 C, to continuously measure the performance of devices for over a year. They will probably continue this testing for several years to characterize the performance of their devices over time. The dynamic aging test, though not typically used for semiconductors is commonly used test to determine quartz oscillator reliability hence an appropriate request from SiTime customers. Similarly, since quartz oscillators and MEMS resonators actually vibrate during use it was necessary to characterize any change in device output when mechanically shocked. Not a typical test for semiconductors, but again an appropriate test for the SiTime part.

Extensive qualification tests, appropriate to the device technology and end application, are necessary to insure product reliability. Ideally existing packaging technology should be used to reduce the required testing. However as this is not always possible, it is best to minimize deviation from off-the-shelf solutions. Due to the complexity of the tests, the time and resources it takes to complete (especially when modifications and retesting may be required), the need to engage customers, and the inevitable technology challenges one can never start package design and qualification early enough.

In “High-reliability Accelerometer and Pressure Sensor Design and Test”, Tom Kwa (MEMS Design and Development Manager, Meggitt Sensing Systems) highlighted the challenges in building and testing high reliability MEMS sensors for use in extreme conditions. He presented three example applications: pacemaker accelerometer, bunker-buster accelerometer, and aircraft tire pressure sensor.

Mr. Kwa started by listing the origins of device unreliability from both mechanical and electrical root causes. Mechanical causes include fracture (due to over-load or stress concentration), stiction (due to humidity or particles), and stress (due to base strain or conditioning). Electrical failure causes include shorts (due to electro-static discharge (ESD) or metal diffusion), opens (due to ESD or metal corrosion), and drift (due to mobile ions, contact surface, or stress relief). For each application, Mr. Kwa listed some of the reliability challenges and provided specific examples of how they avoided these potential causes of low reliability.

Pacemakers provide a challenge due to their expected service life as well as the high cost and risk of replacement. One of Meggitt’s Endevco brand accelerometers has been in use in pacemakers for over fifteen years without any field returns. Mr. Kwa then showed specific features of an accelerometer designed to prevent both over-range damage and stiction. Some of the extreme test conditions and results shown for this particular sensor for extreme conditions included acceleration at 1,400g, shock at 2,300g, and temperature testing from -55 to 125 C.

Fuzing applications, such as the detonation of bunker-busting munitions, require the sensor to not only survive the initial impact(s) but to properly sense the correct events. Some bunker-busting munitions “count” or sense the number of reinforced floors penetrated and only detonate after penetrating a minimum number to improve the ability to reach the desired target. The sensor needs to be designed to avoid mechanical damage from the over-range input of the impacts and be able to immediately return to normal operation without recalibration. Any deformation of the MEMS element from the shock needs to be minimal to avoid malfunction.

Meggitt has developed specialized test equipment to provide the extreme high force shocks required to test sensors operating under these conditions and sells these items to others. Their comparison shock calibrator provides up to 10,000g while their Hopkinson Bar system can test in the range of 20,000g to 240,000g. Meggitt also has a system to test at even higher forces. 

Lastly, the aircraft tier pressure sensor application was used to illustrate how not only the design, but the materials and fabrication processes affect die stability and reliability. In order to sufficiently stress these pressure sensors Meggitt tests the sensors from -55 to 260 C with very fast changes in temperature. By subjecting the sensors to conditions similar to those seen in flight, the design, materials, and processes can be evaluated and adjusted as required to meet the extreme conditions.

With care, MEMS sensors can be built to perform reliably under extreme conditions in “mission critical” applications. This requires signficant characterization and reliability testing along with extensive in-production testing to achieve the required quality levels. All these efforts definitely add to the cost of the products but Meggitt has demonstrated that it can be done reliably. 

Stay tuned for the final summary of MEMS Testing and Reliability 2012 to be posted shortly.

Can reliability and production testing keep pace with the explosive growth in  microelectromechanical system (MEMS) based product volumes? Soon it will be the rare consumer product that does not include a MEMS device bringing us closer to the possibility of a $1 trillion MEMS market. In order to achieve greater adoption of the technology, cost and quality goals will need to be met through testing and reliability. This was the focus of the MEMS Testing and Reliability 2012 conference produced by MEMS Journal and MicroElectronics Packaging and Test Council (MEPTEC).

Session 2

Mårten Vrånes (Director of Consulting Services, MEMS Journal) in “A Test-centric Approach to MEMS ASIC Development” discussed alternatives to the traditional co-design of the MEMS element and application specific integrated circuit (ASIC). As many MEMS devices require an ASIC to control and/or sense the MEMS element the most logical approach is to design both parts in parallel. However the scope of such a development effort is often beyond the resources – both in terms of talent and funding – for many companies especially startups.

Mr. Vrånes started with the challenges and pitfalls of ASIC development for MEMS devices. There are challenges regardless of the path chosen: a full custom design or one based upon intellectual property (IP) block design. With custom design the biggest risk is often the resources, money and people, along with the time required to complete a design. There may also be hidden IP infringement issues and unknown testability issues with a new design. Using IP blocks, if restricted to proven IP blocks already in production, reduces the risk. But this approach may carry risks such as fab dependencies, limited testability features, availability, and price issues.

Both approaches also carry the risk of ASIC to MEMS device “fit”. How well does the electrical signals that either control (for an actuator) or sense (for a sensor) a MEMS element match the ASIC circuitry? For example, if the MEMS element provides too weak of an electrical output for which the ASIC doesn’t have the proper amplification the two devices may not work well together. When there is a mismatch between the two, either the ASIC or the MEMS element needs to be redesigned. In the worst case, both require a redesign. And the redesign cost and effort may cause the project or even the company to fail. Several examples were provided in which seemingly minor changes or low risk modifications had significant impacts to the projects.

Three approaches to enable building and characterizing the MEMS element prior to completing the ASIC design were presented. These were the use of an off-the-shelf sensor signal conditioner (SSC) IC, stepwise design, and use of a field programmable gate array (FPGA).

An SSC is a multipurpose programmable ASIC designed to support many types of common MEMS devices especially sensors. For a sensing MEMS it may have programmable measurement circuits to make highly accurate capacitance or voltage measurements of the MEMS device which are then processed by an on-board analog-to-digital converter. Since SSC are typically purchased from an outside company they may not be as low cost as an ASIC in extremely high volume. Using an SSC can remove considerable development risk and speed time to proof of concept or market. For lower volumes, perhaps less than ten million devices a year, using an SSC may in fact be lower cost than a custom ASIC. The main value of an SSC is allowing a resource limited team, such as a startup, to focus on developing the MEMS device and making a working product without incurring the ASIC development effort or cost upfront.

In stepwise design, only the analog “front end” – i.e. the desired circuitry that directly connects or interfaces to the MEMS element to make or control the analog signals – of the eventual ASIC is designed and fabricated using a multi-project wafer build. This allows the design team to focus on the most critical, and typically the most challenging, part of the ASIC design. Using a multi-project build provides an economical means to quickly obtain a small quantity of ICs to use to debug both the critical portions of the ASIC design and the MEMS element. The rest of the functions of the final ASIC device is then implemented with a field programmable gate array (FPGA).

The last approach is to use a FPGA to provide all the functionality of the typical ASIC used with a MEMS element. In some cases, the analog circuitry required can be supported by existing FPGAs. There is also discussion about FPGA suppliers building MEMS development platforms in the future. However, it is more likely that MEMS product development companies will need to partner with one or more FPGA suppliers to obtain the needed circuitry to support MEMS devices. As volumes increase, it is more likely that this market segment will gain the attention of the FPGA companies.

With all three approaches – SSC, stepwise, and (full) FPGA – these provide the critical elements required to debug and characterize the MEMS element without the commitment and cost of a full ASIC development. These approaches may also be suitable for delivering low to medium volume products at a reasonable cost point. Therefore these solutions not only reduce the overall project risk profile and cost of a high volume product, they provide a path for developing innovative products that might not have a sufficient return on investment (ROI) to proceed when including the cost of ASIC development.

In “Autonomous Self-calibration of MEMS”, Jason Clark (Assistant Professor of Electrical and Computer Engineering and Assistant Professor of Mechanical Engineering, Purdue University) described the challenges of measuring MEMS devices and the need for autonomous self-calibration. MEMS devices tend to be very precise producing repeatable measurements but have low intrinsic accuracy. No two MEMS devices behave exactly the same due to variations in the manufacturing process. Therefore they require calibration to adjust the output(s) to the correct (reference) value to provide meaningful data and to correlate between devices. (Please see accuracy versus precision for the difference between these two concepts since they are often confused.)

These challenges in making measurements and performing calibration during development and in production are significant limiters to the development of new MEMS and nanotechnology. The lack of standards in performing measurements on this scale also make progress challenging. In addition, Professor Clark reported that one study from the National Institute of Standards and Technology (NIST) attributes 30 to 40% of the cost of manufacturing is due to calibration and calibration related issues.

In addition to variation in the actual MEMS devices, there is also the uncertainty when using external instruments to measure them. An example given is that of using atomic force microscopy (AFM) which determines force by using a laser to measure the displacement of a cantilever. The force (F) is equal to the beam stiffness (k) times the displacement of the cantilever (x). [F=kx] If both the beam stiffness and displacement measurements have an uncertainty of +/- 10% the overall measured force will have an uncertainty of +/- 20% which is a very wide distribution. Typical measurement uncertainties may be significantly higher depending on the specific measurements made and the equipment used leading to even larger uncertainties in the measurements. Simply put measurements at this scale are very challenging.

During a lunch discussion with Professor Clark, someone was curious about how measurement error “stacks”. I recommended the authoritative classic on this subject “An Introduction to Error Analysis: The Study of Uncertainties in Physical Measurements” by John R. Taylor. Professor Clark also recommended this book that is known to many engineering students as the “train book” due to distinctive train crash on the cover. If you are not familiar with this book and you are involved in measurement or test, you should be.

MEMS fabrication processes variation also provides challenges in modeling the designs. Many fabrication processes vary noticeably from the computer aided design (CAD) artwork. For example, even though photolithography masks have sharp corners the actual shape produced has rounded corners. And side edges tend to taper which become pronounced as layer thicknesses increase so the cross section of a beam is not square but closer to a trapezoid. The shape of structures may also change depend on the closeness to other structures. All of these variations are difficult to predict accurately and may vary from unit to unit depending on exact processing conditions. When the design CAD model is used for simulation these variations are typically not accounted for thereby reducing the accuracy of the simulation. For the most accurate results, physical measurements of devices need to be made and used as the basis of the simulation. Care must be taken since the measurements may have a high degree of uncertainty which may lead to significant simulation errors.

To solve these challenges, Professor Clark invented the field of electro micro metrology (EMM) which permits the measurement of dozens of mechanical properties in terms of electrical measurands. EMM is based upon the construction of test structures on the MEMS device which are designed to be measured electrically. Taking advantage of fabrication processes with extremely high localized uniformity – meaning that all the features in a given area will be processed the same –  two EMM structures are built with one asymmetric feature. This permits the calculation of the mechanical property of interest by comparing the ratio of the electrical measurements. Since the structures are uniform within the same device the process to design variation is eliminated by comparing the two structures. And if the electrical measurement is precise the need for accuracy is eliminated by using the ratio of the measurements.

Professor Clark provided a detailed comb drive example that had asymmetric distances to a central stop. By exciting the drive and measuring displacement and corresponding capacitance for each side he was able to reliably calculate the force, stiffness, mass, viscous damping, and quality factor. This methodology provides meaningful data for calibration of the device to significantly improve the device’s accuracy. The algorithms to perform self-calibration of the MESM device could be included in the sensing ASIC. He showed another example of a structure that once it is self-calibrated can be used to accurately calibrate AFMs.

Adding appropriate test structures in each device permits characterization and modeling accuracy to be improved and allows devices to self-calibrate without the need for external measurements. Using asymmetric structures that reference each other can remove the variably of the fabrication process to provide every greater accuracy.

Stay tuned for additional summaries of MEMS Testing and Reliability 2012 to be posted shortly.

It was my pleasure to attend the MEMS Testing and Reliability 2012 conference to see the considerable progress made in these areas as microelectromechanical system (MEMS) based product volumes accelerate. We may soon get to the point where it will be the rare consumer product that does not include a MEMS device bringing us closer to the possibility of a $1 trillion MEMS market. But in order to achieve greater adoption of the technology, cost and quality goals will need to be met through testing and reliability, the focus of this conference produced by MEMS Journal and MicroElectronics Packaging and Test Council (MEPTEC).

Session 1

Mario Correa (MEMS Test Engineering Manager of Fairchild Semiconductor) started with “Evolution of MEMS Test Solutions” reviewing how test equipment and processes have evolved from the 1960′s to today. There have been major changes to test methods developed for non-MEMS sensors first used with military and aerospace MEMS sensors in the late 1960′s where the annual volume was measured in thousands of units to those used today for over three billion units shipped yearly to the consumer electronics market. It has been a challenge keeping up with the high triple digit growth rates from 2009 to 2012 including gyroscopes +189%, microphones +347%, and digital compasses +778%. MEMS accelerometers grew “only” +78% during this period. (Growth data per Yole)

These changes include the evolution of the test system from a purpose built single device tester to modular high parallelism multisite testers. As the parallelism increased, the number of required stimuli also increased. Older testers for an accelerometer or gyroscope originally only tested one axis a time which was fine since these devices only measured one axis. As three axes sensors become the norm, three axes testers had to be developed to avoid having to test these parts three times, once for each axis. And now that six axes devices – three gyroscope axes plus three accelerometer axes – are extremely common with even greater axes devices (some have nine with the addition of magnetic sensors) on the way, test system complexity has grown to accommodate these needs.

As the system complexity has increased, so has the speed of these systems growing from less than 100 units per hour (UPH) in the late 1990′s to upwards of 7,500 to 10,000 UPH today. While the total capital cost of these systems has increased by an order of magnitude, the effective cost per UPH per axis has dropped by two orders of magnitude from $2,700 to $30.

Since many of these test systems operate on devices in their final packaged form, there has been an increased demand to test the MEMS elements while still on wafer to avoid the cost of packaging a bad device. Many MEMS sensors also include a fairly costly application specific integrated circuit (ASIC) increasing the need to know that the MEMS and the ASIC are both good before connecting them together and encapsulating in the final package. Since most MEMS elements are singulated and attached individually to either the ASIC die or to a common substrate, bad MEMS elements or bad ASIC die can be skipped and removed from the process flow. 

For inertial sensors that can be electrostatically actuated, or for those to which a test structure can be added to move the sensor electrostatically, dynamic wafer testing has been developed. Dynamic wafer test applies an electrical stimulus pulse to move the sensing elements and then measures the resulting movement of the sensor as it resonates and decays. Even though this stimulus is not the same as the device will see in final test or actual usage, the response “signature” can be correlated to “good” and “bad” parts. Companies that offer technology to test the MEMS elements while still on wafer prior to electronic integration and packaging include Solidus Technologies and SPEA.

Lastly, there is an increasing trend from device specific test equipment towards a generalized test cell approach similar to those used in final (semiconductor) package test. Different companies such as Focus Test, SPEA, Multitest, and Teradyne offer part “handlers” that move individual parts to groups of parts (in tray or strip with as many as 72 or 144 sites tested in parallel), stimulus units, and testers that can be combined and reconfigured to test a wide range of products.

In “Applying the CMOS Test Flow to MEMS Manufacturing”, Mike Daneman (Manger of MEMS Operations, InvenSense) described the different approach InvenSense has taken to test the almost 100 million parts a year they ship.

With their unique Nasiri-Fabrication (NF) process the MEMS device wafer is directly attached to the ASIC wafer using wafer bonding to become the package. Like other processes, the ASIC wafer is fabricated and wafer tested as usual with typically high yields. On the MEMS device wafer they only measure a small set of parameters during test, without the need to stimulate the sensor, to determine if the quality level is acceptable to use. Extensive testing of each MEMS device is not warranted prior to wafer bond since they have to use the entire wafer with no provision to discard bad MEMS elements. Fortunately, they have improved the yield of their devices to the level at which direct wafer to wafer bonding makes economic sense.

After the wafers are bonded together, the combined ASIC and MEMS dies are singulated and encapsulated in the final package. For final test they use custom-built test systems designed for high throughput by mechanically stimulating and testing a large number of parts in parallel. Surprisingly, these systems have a bowl-feeder which are often used for very high volume low-cost parts but aren’t often used on such high value parts which typically require traceability. InvenSense achieves the needed traceability back to the die locations on the original ASIC and MEMS wafers through individual serial numbers programmed into each ASIC during wafer test. They use special test and calibration routines designed into the ASIC to improve the efficiency of the test process and to lower test cost. The ASIC can also measure test structures on the MEMS device to further optimize the test process and device performance. Traceability through the entire process from ASIC wafer and MEMS wafer to final part allowed them to quickly improve their yields to further reduce costs.

By integrating both the design of their device and manufacture processes for ASIC and MEMS alike – which are often designed separately and fabricated without consideration to the other parts – InvenSense was able to make tradeoffs between each element to provide greater overall efficiency and lower cost. This allows them to successfully ship such large quantities of parts and to make their process available to others to develop innovative MEMS devices.

Stay tuned for additional summaries of MEMS Testing and Reliability 2012 to be posted shortly.