March 14, 2013
Sunset over Phoenix, Arizona during BiTS Workshop
As the Burn-in & Test Strategies (BiTS) Workshop 2013 fades into the sunset (queue the music), here is a round-up of the highlights. There were gun fights in the corral as well as technical questions for the presenters. The saloon girls and gunfighters took an edge off of the “geek” factor. This year over three hundred fifty people come to the “Circle BiTS Ranch” (aka the Hilton in Mesa, Arizona) for the premier conference focused on what is new and next for semiconductor test tooling and strategy. Oh, did I mention that the theme this year was Western?
This was the 14th annual BiTS Workshop, which has achieved the perfect conference trifecta of Read the rest of this entry »
June 26, 2012
Here are the highlights from Session Three “Probe Potpourri” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 11, 2012.
Larry Levy (FormFactor, Inc.), “Is Parametric Testing About To Enter a Period of Growth and Innovation?”:
Upwards of one thousand facilities perform parametric wafer testing (based on 2009 market data) with over a third of these using obsolete test equipment. There have been no really new testers in several years – Agilent still has their 40xx series and Keithley has their S530 tester. And several companies have exited the market and some companies (including Keithley) are no longer supporting older models of testers. Since parametric testing remains an essential process, this has forced a high number of these facilities to use obsolete equipment or find other approaches. A few companies are going as far as using an Advantest 93000, a significantly more expensive and highly sophisticated digital tester, for parametric test. [Updated to clarify Keithley's status.]
Parametric testing can be divided into three categories: in-line, end of line (EOL), and quality and reliability. In-line testing is Read the rest of this entry »
November 28, 2011
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Back for the second year (with a minor name change), the Silicon Valley Test Workshop is an unpolished gem. Looking past the rough edges (minor logistical issues), what really shines through is the interaction of the participants. This conference really has Read the rest of this entry »
October 31, 2011
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The MEMS Testing and Reliability 3rd Annual Conference gets high marks: excellent speakers focused on an emerging topic and it was large enough to have “critical mass” while allowing everyone to interact. It was well produced by MEMS Investor Journal and MEPTEC.
My presentation, “Semiconductor Wafer Test Technology and Trends: Lessons for MEMS Test Engineers“, covered the differences between testing semiconductors and microelectromechanical systems (MEMS). I reviewed the progress in test technology over the last fifty plus years, from simple cantilever probe cards to large full wafer contact probe cards, developed to reduce the cost of test.
I discussed lower cost solutions that appear counter-intuitive since they require increased technical and operational complexity. Challenges of testing MEMS devices while still on wafer (prior to packaging and singulation) were discussed along with a review of MEMS solutions at this year’s IEEE Semiconductor Wafer Test Workshop.
With the proper skills, experience, and perspective it is possible to avoid “re-inventing the wheel” and to develop the best strategy to profitably introduce new technologies to high volume manufacturing.
June 17, 2011
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As the final presenter at this week’s IEEE Semiconductor Wafer Test Workshop (SWTW), I outlined how critical it is to understand the true cost of a product’s architecture in “Probe Card Cost Drivers from Architecture to Zero Defects“. Without a proper understanding of these costs – especially for fully custom high technology products such as wafer test probe cards – it is impossible to maintain a sufficient gross margin. Gross margin is essential to maintain the health of a company and to fund the research & development required for innovation.
Many companies in the semiconductor test market have entered a period that Steve Newberry identified in his 2008 speech “Semiconductor Industry Trends: The Era of Profitless Prosperity?” that parallels the aluminum industry in the 1970′s. And without the means to fund innovation, companies have no future especially when faced with the double threat of Moore’s Law – increasingly harder technical requirements delivered at lower cost.
Yes, there were a few in the audience who appeared pleased since they are confident that their products are on the right path. There were others who may have been upset based upon their company’s direction. I would argue that a proper diagnosis – regardless of how disturbing – is essential to drive the proper cure.
There is plenty of opportunity in the test market and reasons for optimism. The key to long term prosperity is to really understand the fundamentals of the business and not be blinded by the technology.
I thank those who stayed for the entire conference and welcome your thoughts below. And I will be posting more about the conference (including my summaries) in the next few weeks.
November 16, 2010
Starting off something new is often challenging and difficult with many unknowns. Kudos to Nick Langston for creating the Silicon Valley Test Conference that was held last week. (November 8 & 9, 2010) It was the first test conference to actually take place in Silicon Valley. And yes there were some minor “bugs” like registration delays and a no-show by the audio visual contractor that should be solved in next year’s Rev 2.0. Even with a few rough edges, the quality of the presentations and the exhibitors shined through to make this a success.
The conference opened with an excellent keynote address by well-known industry expert Read the rest of this entry »
May 17, 2010
… and how it impacts your bottom line!
A poorly implemented semiconductor test cell may pass integrated circuit (IC) parts that are either defective or have marginal performance. They can cause the electronic devices in which they will be assembled to either malfunction or completely fail. However, two other conditions require evaluation. Having false negative test “escapes” is expensive in terms of final product test failures, warranty costs, customer dissatisfaction, etc. In turn, the false positive test escapes needs to be balanced against the cost of false negative failures where otherwise good parts fail the tests and are discarded. Test engineers, product managers, quality engineers, and operational managers needs to make either implicit or explicit decisions as to the proper balance in adjusting the test limits. The goal is to cost effectively approach “zero defects” without “throwing out the baby with the bath water”.
A test process generally categorizes the item or device being tested as “pass” or “fail”. Sometimes passing devices are graded (typically by speed or other desired quality) and failing devices are often grouped by failure mode. “Coverage” is how well a particular test process measures the functionality and specifications of a given device. If every feature and specification is tested then it is said to have 100% test coverage. However, exhaustive testing is usually expensive due to long test times which translates in to operational costs including the depreciation of the test system and greater test setup complexity (equipment and development cost). Sometimes complete coverage is not possible or practical so there needs to be a trade-off between coverage and cost.
Read the rest of this entry »