IEEE Semiconductor Wafer Test Workshop – Power Probing – Session Three (Monday)

July 12, 2011

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Here are the highlights from Session Three – “Power Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.

Michael Huebner, FormFactor, “A Hot Topic: Current Carrying Capacity, Tip Melting and Arcing”:

Power consumption per dynamic random-access memory (DRAM) is increasing to as high as 400 mA or more under normal test conditions. At the same time the number of DRAMs being tested in parallel – and sharing the same power supply – is increasing. Therefore, the risk of current damage to probes is increasing.

Two distinct, but related concerns are Read the rest of this entry »

Leave a Comment » | DRAM, IEEE, Probe Card Metrology Tools, Probe Cards, Semiconductor Test, Semiconductor Wafer Test Workshop, Simulation | Tagged: , , | Permalink
Posted by Ira Feldman

IEEE Semiconductor Wafer Test Workshop – Area Array Probing – Session Eight (Wednesday)

June 29, 2010

Here are the highlights from Session Eight – Area Array Probing of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 9th.

Senthil Theppakuttai, SV Probe, “Probing Assessment on Fine Pitch Copper Pillar Solder Bumps”:

Flip chips devices are shrinking from 150 µm to 35 µm pitch interconnect. At 150 µm pitch solder balls formed by deposition or electroplating, and stud bumping are typically found.  However at tighter pitches down to 35 µm, copper (Cu) pillars with solder caps are the preferred termination. The copper pillars solve electro-migration issues and mechanical/thermal (CTE) mismatch found with solder balls and stud bumping.
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1 Comment | Automatic Test Equipment (ATE), Full Wafer / 1 Touch Down Test, Multi Layer Ceramics (MLC), Printed Circuit Boards (PCB), Semiconductor Test, Semiconductor Wafer Test Workshop, Simulation, Space Transformers | Permalink
Posted by Ira Feldman

IEEE Nanotechnology Symposium – Session 7 – Nano-Enabled Energy II

May 21, 2010


Here are the highlights from Session 7 – Nano-Enabled Energy II from day two of the IEEE San Francisco Bay Area Nanotechnology Council 6th Annual Symposium“Nanotechnology: State of the Art & Applications”

Presentation archive for talks not linked below. Updated as the council receives the presentations.

Dr. David Predergast, Lawrence Berkeley National Laboratory (LBNL) Molecular Foundry, “Nature of Nano-Scale Interfaces and Mechanisms for Solar Energy Conversion.”

Leave a Comment » | IEEE, Nanotechnology, Simulation, Solar | Tagged: , | Permalink
Posted by Ira Feldman

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