Michael Splinter (Applied Materials) - Relative industry cost improvements and volumes.
I hope that my summaries of the first day of SEMI Industry Strategy Symposium (ISS) 2012 in
provided useful insights to the economic roller coaster that is the semiconductor market and its equipment and material supply chain. There have also been several good reports Read the rest of this entry »
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2.5D/3D Stacked Integrated Circuits (ICs), 450 mm wafers, Economics, Moore's Law, SEMI, Semiconductor Capital Equipment (CAPEX), Semiconductors | Tagged: 2.5D/3D Stacked Integrated Circuits (ICs), 450 mm wafers, Economics, Moore's Law, SEMI, Semiconductor Capital Equipment (CAPEX), Semiconductors | 
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Posted by Ira Feldman
After a gloomy first session focused on world economics at SEMI Industry Strategy Symposium (ISS) 2012, Session 2 – Semiconductor Markets was significantly more upbeat.
Stephen G. Newberry (Vice Chairman of the Board, Lam Research Corporation) started off with a way forward in Read the rest of this entry »
Leave a Comment » | 2.5D/3D Stacked Integrated Circuits (ICs), 450 mm wafers, Economics, Moore's Law, SEMI, Semiconductor Capital Equipment (CAPEX), Semiconductors | Tagged: 2.5D/3D Stacked Integrated Circuits (ICs), 450 mm wafers, Economics, Moore's Law, SEMI, Semiconductor Capital Equipment (CAPEX), Semiconductors | Permalink
Posted by Ira Feldman
Like the roller coaster ride that is the semiconductor industry, the SEMI Industry Strategy Symposium (ISS) 2012 had its share of ups, downs, twists, and turns. Semiconductor Equipment and Materials International – better known as SEMI – as the industry association of suppliers to semiconductor manufacturers has held this annual conference in early January for thirty five years to provide updates on business conditions and technology roadmaps to enable SEMI members to plan for the coming year. The conference was packed with senior management paying close attention to the industry leaders, analysts, and customer presenters. All of the presentations, even the most poorly disguised sales pitch or infomercial, contained several valuable insights.
In his keynote presentation “Technology Law Still Delivers“, William Holt (Senior Vice President; General Manager, Technology & Manufacturing Group, Intel Corporation) opened the conference with much optimism based upon Read the rest of this entry »
Leave a Comment » | Economics, SEMI, Semiconductor Capital Equipment (CAPEX), Semiconductors | Tagged: Economics, SEMI, Semiconductor Capital Equipment (CAPEX), Semiconductors | Permalink
Posted by Ira Feldman
…To make sense of the big picture, one needs to follow the money and then head to China.
Ed Pausa the primary author of PricewaterhouseCooper’s (PwC) recently published report “Continued Growth: China’s Impact on the Semiconductor Industry – 2011 Update” provided an overview at this month’s MEPTEC luncheon. His presentation was a helpful tour to start digesting this impressive report, now it its seventh annual update. The report runs 112 pages in length and is packed with figures, data and most importantly analysis. Building a cohesive picture from many disparate data sources is a major undertaking and PwC should be applauded for making available this excellent work.
After listening to this presentation and reading the report, I find two items that really stand out as primary market forces. Unraveling the convoluted web of the semiconductor supply chain to examine these items will lead to greater understanding of the industry. They are, Read the rest of this entry »
Leave a Comment » | Marketing, MEPTEC, Semiconductor Capital Equipment (CAPEX), Semiconductors | Tagged: Marketing, MEPTEC, Semiconductor Capital Equipment (CAPEX), Semiconductors | Permalink
Posted by Ira Feldman
Here are the highlights from Session Five – “Spring Pin Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 14, 2011.
Brandon Mair, Texas Instruments, “WSP-Wafer Socket Probe for Flip Chip Applications“:
Wafer socket probe (WSP) technology has demonstrated better physical and electrical performance and lower cost of ownership (COO) than traditional vertical probe cards for testing wafer level chip scale packages (WLCSP) at 0.4 mm (400 µm) pitch. These WSP probe heads are typically built Read the rest of this entry »
2 Comments | Cost of Test, IEEE, Probe Cards, Semiconductor Capital Equipment (CAPEX), Semiconductor Test, Semiconductor Wafer Test Workshop | Tagged: IEEE | Permalink
Posted by Ira Feldman
Click image to download presentation
As the final presenter at this week’s IEEE Semiconductor Wafer Test Workshop (SWTW), I outlined how critical it is to understand the true cost of a product’s architecture in “Probe Card Cost Drivers from Architecture to Zero Defects“. Without a proper understanding of these costs – especially for fully custom high technology products such as wafer test probe cards – it is impossible to maintain a sufficient gross margin. Gross margin is essential to maintain the health of a company and to fund the research & development required for innovation.
Many companies in the semiconductor test market have entered a period that Steve Newberry identified in his 2008 speech “Semiconductor Industry Trends: The Era of Profitless Prosperity?” that parallels the aluminum industry in the 1970′s. And without the means to fund innovation, companies have no future especially when faced with the double threat of Moore’s Law – increasingly harder technical requirements delivered at lower cost.
Yes, there were a few in the audience who appeared pleased since they are confident that their products are on the right path. There were others who may have been upset based upon their company’s direction. I would argue that a proper diagnosis – regardless of how disturbing – is essential to drive the proper cure.
There is plenty of opportunity in the test market and reasons for optimism. The key to long term prosperity is to really understand the fundamentals of the business and not be blinded by the technology.
I thank those who stayed for the entire conference and welcome your thoughts below. And I will be posting more about the conference (including my summaries) in the next few weeks.
2 Comments | Automatic Test Equipment (ATE), Cost of Test, DRAM, FLASH Memory, Full Wafer / 1 Touch Down Test, High Volume Manufacturing (HVM), IEEE, Market Analysis, Multi Layer Ceramics (MLC), My Presentations, Photolithography, Printed Circuit Boards (PCB), Probe Card Metrology Tools, Probe Cards, Product Management, SEMI, Semiconductor Capital Equipment (CAPEX), Semiconductor Test, Semiconductor Wafer Test Workshop, Semiconductors, Space Transformers, Test Engineers | Tagged: DRAM, FLASH Memory, IEEE, SEMI, Semiconductors | Permalink
Posted by Ira Feldman
Last week I was very busy visiting the combined SEMICON West and Intersolar North America trade shows in San Francisco. I had numerous meetings in addition to visiting the show floors and attending the excellent presentations. Based upon the lackluster show last year – I’ve heard some use “abysmal” to describe it – I almost hesitated to attend.
I’m happy to report that this year’s show was significantly better with a much more positive attitude and energy. SEMI’s preliminary attendance figure (for the combined show) is 29,461 which is up 32% from last year’s 17,048 verified attendance. This is significantly higher than both organizers expected. Intersolar had expected 1,600 visitors but had over twice as many. (The final numbers will be out in about two weeks in the “Post Show” report.)
Having attended for more than 15 years, Read the rest of this entry »
2 Comments | Intersolar, SEMI, SEMICON West, Semiconductor Capital Equipment (CAPEX), Semiconductor Test, Solar | Tagged: SEMI | Permalink
Posted by Ira Feldman
The 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW) started this evening. Rumor has it that attendance is over 240 this year which is a vast improvement over last year’s 160 or so attendees. At the peak the conference had almost hit 600. Things started off well with a reception where I had the chance to catch up with many industry friends and colleagues.
After dinner, Jerry Broz the General Chair kicked things off with the “Probe Year in Review”. In summary:
Read the rest of this entry »
Leave a Comment » | Automatic Test Equipment (ATE), Clean Tech (Green), IEEE, Probe Cards, Semiconductor Capital Equipment (CAPEX), Semiconductor Test, Semiconductor Wafer Test Workshop, Solar | Tagged: IEEE | Permalink
Posted by Ira Feldman
Here are the highlights from Session 5 – Nano-Processes from day two of the IEEE San Francisco Bay Area Nanotechnology Council 6th Annual Symposium“Nanotechnology: State of the Art & Applications”
Note: I will post the the link for the slides once it becomes available.
Dr. Hans Stork, VP and CTO Applied Materials, “Nanotechnology in Semiconductor Industry.”
Leave a Comment » | 3-D Microstructures, High Volume Manufacturing (HVM), IEEE, Manufacturing, Nanotechnology, Photolithography, Semiconductor Capital Equipment (CAPEX) | Tagged: IEEE, Nanotechnology | Permalink
Posted by Ira Feldman
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