April 26, 2012
Some consider the many of billions of dollars invested in the semiconductor supply chain to be huge bets on yet to be proven technology and future business. Even if you take a strict view of this as simply business it is possible to learn something from gambling.
The Atlantic tells the fascinating story of how Don Johnson took Atlantic City casinos for $15 M playing blackjack. Last year he won $5 M from Borgata in February, $4 M from Caesars in March, and $6 M from Tropicana in April. This wasn’t luck and he wasn’t card counting. How did he do this and how does this connect to semiconductors and Apple?
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2.5D/3D Stacked Integrated Circuits (ICs), 450 mm wafers, Apple, Design Cycles, Economics, Management, Mobile Devices, Post PC Era, SEMI, Semiconductors | Tagged: 2.5D/3D Stacked Integrated Circuits (ICs), 450 mm wafers, Apple, Design Cycles, Economics, Management, Mobile Devices, Post PC Era, SEMI, Semiconductors | 
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Posted by Ira Feldman
February 2, 2012
Michael Splinter (Applied Materials) - Relative industry cost improvements and volumes.
I hope that my summaries of the first day of SEMI Industry Strategy Symposium (ISS) 2012 in
provided useful insights to the economic roller coaster that is the semiconductor market and its equipment and material supply chain. There have also been several good reports Read the rest of this entry »
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Posted by Ira Feldman
January 25, 2012
After a gloomy first session focused on world economics at SEMI Industry Strategy Symposium (ISS) 2012, Session 2 – Semiconductor Markets was significantly more upbeat.
Stephen G. Newberry (Vice Chairman of the Board, Lam Research Corporation) started off with a way forward in Read the rest of this entry »
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Posted by Ira Feldman
January 23, 2012
Like the roller coaster ride that is the semiconductor industry, the SEMI Industry Strategy Symposium (ISS) 2012 had its share of ups, downs, twists, and turns. Semiconductor Equipment and Materials International – better known as SEMI – as the industry association of suppliers to semiconductor manufacturers has held this annual conference in early January for thirty five years to provide updates on business conditions and technology roadmaps to enable SEMI members to plan for the coming year. The conference was packed with senior management paying close attention to the industry leaders, analysts, and customer presenters. All of the presentations, even the most poorly disguised sales pitch or infomercial, contained several valuable insights.
In his keynote presentation “Technology Law Still Delivers“, William Holt (Senior Vice President; General Manager, Technology & Manufacturing Group, Intel Corporation) opened the conference with much optimism based upon Read the rest of this entry »
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Posted by Ira Feldman
June 17, 2011
Click image to download presentation
As the final presenter at this week’s IEEE Semiconductor Wafer Test Workshop (SWTW), I outlined how critical it is to understand the true cost of a product’s architecture in “Probe Card Cost Drivers from Architecture to Zero Defects“. Without a proper understanding of these costs – especially for fully custom high technology products such as wafer test probe cards – it is impossible to maintain a sufficient gross margin. Gross margin is essential to maintain the health of a company and to fund the research & development required for innovation.
Many companies in the semiconductor test market have entered a period that Steve Newberry identified in his 2008 speech “Semiconductor Industry Trends: The Era of Profitless Prosperity?” that parallels the aluminum industry in the 1970′s. And without the means to fund innovation, companies have no future especially when faced with the double threat of Moore’s Law – increasingly harder technical requirements delivered at lower cost.
Yes, there were a few in the audience who appeared pleased since they are confident that their products are on the right path. There were others who may have been upset based upon their company’s direction. I would argue that a proper diagnosis – regardless of how disturbing – is essential to drive the proper cure.
There is plenty of opportunity in the test market and reasons for optimism. The key to long term prosperity is to really understand the fundamentals of the business and not be blinded by the technology.
I thank those who stayed for the entire conference and welcome your thoughts below. And I will be posting more about the conference (including my summaries) in the next few weeks.
2 Comments | Automatic Test Equipment (ATE), Cost of Test, DRAM, FLASH Memory, Full Wafer / 1 Touch Down Test, High Volume Manufacturing (HVM), IEEE, Market Analysis, Multi Layer Ceramics (MLC), My Presentations, Photolithography, Printed Circuit Boards (PCB), Probe Card Metrology Tools, Probe Cards, Product Management, SEMI, Semiconductor Capital Equipment (CAPEX), Semiconductor Test, Semiconductor Wafer Test Workshop, Semiconductors, Space Transformers, Test Engineers | Tagged: DRAM, FLASH Memory, IEEE, SEMI, Semiconductors | Permalink
Posted by Ira Feldman
July 22, 2010
Last week I was very busy visiting the combined SEMICON West and Intersolar North America trade shows in San Francisco. I had numerous meetings in addition to visiting the show floors and attending the excellent presentations. Based upon the lackluster show last year – I’ve heard some use “abysmal” to describe it – I almost hesitated to attend.
I’m happy to report that this year’s show was significantly better with a much more positive attitude and energy. SEMI’s preliminary attendance figure (for the combined show) is 29,461 which is up 32% from last year’s 17,048 verified attendance. This is significantly higher than both organizers expected. Intersolar had expected 1,600 visitors but had over twice as many. (The final numbers will be out in about two weeks in the “Post Show” report.)
Having attended for more than 15 years, Read the rest of this entry »
2 Comments | Intersolar, SEMI, SEMICON West, Semiconductor Capital Equipment (CAPEX), Semiconductor Test, Solar | Tagged: SEMI | Permalink
Posted by Ira Feldman
