March 14, 2013
Sunset over Phoenix, Arizona during BiTS Workshop
As the Burn-in & Test Strategies (BiTS) Workshop 2013 fades into the sunset (queue the music), here is a round-up of the highlights. There were gun fights in the corral as well as technical questions for the presenters. The saloon girls and gunfighters took an edge off of the “geek” factor. This year over three hundred fifty people come to the “Circle BiTS Ranch” (aka the Hilton in Mesa, Arizona) for the premier conference focused on what is new and next for semiconductor test tooling and strategy. Oh, did I mention that the theme this year was Western?
This was the 14th annual BiTS Workshop, which has achieved the perfect conference trifecta of Read the rest of this entry »
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BiTS Workshop, Cost of Test, DRAM, Interconnectology, Load Boards, Memory Technology, Moore's Law, More than Moore, My Presentations, Packaging (Semiconductor), Printed Circuit Boards (PCB), Probe Cards, Semiconductor Capital Equipment (CAPEX), Semiconductor Test, Semiconductors, Spring Pins, Test Engineers | Tagged: BiTS Workshop, Cost of Test, DRAM, Interconnectology, Load Boards, Memory Technology, Moore's Law, More than Moore, My Presentations, Packaging (Semicondcutor), Printed Circuit Boards (PCB), Probe Cards, Semiconductor Capital Equipment (CAPEX), Semiconductor Test, Semiconductors, Spring Pins, Test Engineers | 
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Posted by Ira Feldman
December 19, 2012
Lego Blocks (flickr: antpaniagua)
My event summary recently published in Chip Scale Review Tech Monthly:
Is 3D semiconductor packaging really the Lego of the integrated circuit (IC) world? It is a great analogy for the range of possible solutions and flexibility provided by different flavors of 3D packaging (2.5D on interposer, 3D, 5.5D, etc.) and “colors” (homogenous and heterogeneous) of die stacks. Plenty of pictures of Legos and scanning electron microscope (SEM) images were shown last week at the RTI International Technology Venture Forum symposium and conference “3-D Architectures for Semiconductor Integration and Packaging”. Presenters clearly articulated the great promise of what could be built with 3D packaging. At the same time, progress towards solving the multitude of challenges to make this technology as pervasive, if not as easy to use and fun, as Legos was discussed.
The challenges span Read the rest of this entry »
Leave a Comment » | 2.5D/3D Stacked Integrated Circuits (ICs), Chip Scale Review, CMOS Imagers, DRAM, Fiber Optic Interconnect, Packaging (Semiconductor), Semiconductor Test, Semiconductors, Standards, Through-Silicon Vias (TSV) | Tagged: 2.5D/3D Stacked Integrated Circuits (ICs), Chip Scale Review, CMOS Imagers, DRAM, Fiber Optic Inteconnect, Packaging (Semicondcutor), Semiconductor Test, Semiconductors, Standards, Through-Silicon Vias (TSV) | Permalink
Posted by Ira Feldman
June 19, 2012
This year’s IEEE Semiconductor Wafer Test Workshop started on Sunday June 10th with a pleasant surprise. Due to a welcomed but unexpected wave of seventy walk-in registrations, there was insufficient seating at the opening dinner. Thankfully the hotel staff quickly adjusted to accommodate these additional guests. Attendance and interest in this year’s workshop was clearly up.
Jerry Broz, general conference chair, welcomed everyone with a brief overview and presented prizes for the first annual golf tournament. We then quickly proceeded with business as Matt Nowak (Senior Director, Advanced Technology, Qualcomm CDMA Technologies) provided the keynote “Emerging High Density 3D Through Silicon Stacking (TSS) – What’s Next?” Mr. Nowak discussed the increased amount of hype within the 3D semiconductor packaging market in the last year with everyone announcing something. And Thru Silicon Vias (TSVs) technology has already been in high volume production for image sensors for several years now but at a significantly lower density than for 3D packaging.
Why the great interest recently in 3D packaging using TSVs today? Three simple reasons: Read the rest of this entry »
Leave a Comment » | 2.5D/3D Stacked Integrated Circuits (ICs), CMOS Imagers, Cost of Test, High Volume Manufacturing (HVM), IEEE, Mobile Devices, Moore's Law, Packaging (Semiconductor), Semiconductor Test, Semiconductor Wafer Test Workshop, Through-Silicon Vias (TSV) | Tagged: 2.5D/3D Stacked Integrated Circuits (ICs), CMOS Imagers, Cost of Test, High Volume Manufacturing (HVM), IEEE, Mobile Devices, Moore's Law, Packaging (Semicondcutor), Semiconductor Test, Semiconductor Wafer Test Workshop, Through-Silicon Vias (TSV) | Permalink
Posted by Ira Feldman
March 15, 2012
Tim Cook introducing Apple's latest iPad
The “Post Personal Computer” (Post PC) era became the hot topic when Tim Cook introduced the latest iPad last week. Yes, calling it a “revolution” is definitely hype that is part of Apple‘s Post PC marketing campaign. Hype aside, it is clear that there has been a marked shift in digital hardware for the consumption of content and communication. The PC – be it a Windows, Mac, or Linux based system – is no longer “the device”. It is now one of many devices including portable music players (dominated by iPods), smart phones (lead by iPhones and Android based systems), and tablets (dominated by iPads). The shift is large and the impact is huge. To understand how big, watch the first three minutes of Mr. Cook’s presentation. Then you will understand why Apple had the largest market capitalization of any US company in February – the numbers are staggering.
Even though many were surprised to learn that we are now “Post PC”, some of us who have been developing strategies for the electronic supply chain have Read the rest of this entry »
Leave a Comment » | 2.5D/3D Stacked Integrated Circuits (ICs), Apple, Consumer Electronics Society, Load Boards, Market Analysis, MEMS, More than Moore, Packaging (Semiconductor), Post PC Era, Printed Circuit Boards (PCB), Probe Cards, Semiconductors | Tagged: 2.5D/3D Stacked Integrated Circuits (ICs), Apple, Consumer Electronics Society, Load Boards, Market Analysis, MEMS, More than Moore, Packaging (Semicondcutor), Post PC Era, Printed Circuit Boards (PCV), Probe Cards, Semiconductors | Permalink
Posted by Ira Feldman
November 28, 2011
Click image to download presentation
Back for the second year (with a minor name change), the Silicon Valley Test Workshop is an unpolished gem. Looking past the rough edges (minor logistical issues), what really shines through is the interaction of the participants. This conference really has Read the rest of this entry »
Leave a Comment » | Semiconductor Test, Probe Cards, Load Boards, Automatic Test Equipment (ATE), Test Engineers, Printed Circuit Boards (PCB), More than Moore, ToThePoint, Packaging (Semiconductor), Moore's Law, Through-Silicon Vias (TSV), 2.5D/3D Stacked Integrated Circuits (ICs), My Presentations | Tagged: 2.5D/3D Stacked Integrated Circuits (ICs), Load Boards, More than Moore, Packaging (Semicondcutor), Printed Circuit Boards (PCV), Probe Cards, Moore's Law, Automatic Test Equipment (ATE), My Presentations, Semiconductor Test, Test Engineers, Through-Silicon Vias (TSV), ToThePoint | Permalink
Posted by Ira Feldman
November 10, 2011
The MEPTEC “2.5D, 3D and Beyond – Bringing 3D Integration to Packaging Mainstream” conference was a mixed-bag. Yes, it is always exciting to hear about new suppliers and progress. But it is disconcerting to realize that the price of progress is an ongoing burden on our industry’s supply chain.
Subramanian Iyer (IBM) and Theresa Sze (Oracle) started with Read the rest of this entry »
Leave a Comment » | 2.5D/3D Stacked Integrated Circuits (ICs), Manufacturing, MEPTEC, Packaging (Semiconductor), Probe Cards, Semiconductor Test, Semiconductors, Through-Silicon Vias (TSV) | Tagged: 2.5D/3D Stacked Integrated Circuits (ICs), Manufacturing, MEPTEC, Packaging (Semicondcutor), Probe Cards, Semiconductor Test, Semiconductors, Through-Silicon Vias (TSV) | Permalink
Posted by Ira Feldman
September 8, 2011
Here are the highlights from Session Six – “Probe Potpourri” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 14, 2011.
Marc Knox, IBM, “The Development of a Flexible and Efficient Chip Thermal Imaging Capability“:
Traditional burn-in systems hold multiple printed circuit boards (PCBs) with one or more devices in burn-in sockets to provide temporary electrical interconnect to a device under test (DUT). These PCBs and sockets are known as “burn-in boards”. And the systems in which they are loaded are “ovens” that permit temperature stressing, sometimes at both hot and cold temperatures, while stimuli are supplied to the chip. The purpose of “burning-in” a device is to screen for infant mortality in an accelerated manner.
The IBM team adapted a burn-in board system to Read the rest of this entry »
Leave a Comment » | 3-D Microstructures, IEEE, Packaging (Semiconductor), Probe Cards, Semiconductor Wafer Test Workshop, Space Transformers | Tagged: IEEE | Permalink
Posted by Ira Feldman
July 26, 2011
Here are the highlights from Session Four – “High Performance Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.
Bob Davis, Rudolph Technologies, “Testing Probe Cards That Contain Complex Circuitry“:
Over time, probe cards have increased in complexity from simple wire cantilever probes to those including passive components and digital control circuits. Some of these digital control circuits may even contain state based logic. At the same time the physical complexity of probe cards have increased in probe and channel counts, probe density, and total probe force. As a result, Read the rest of this entry »
Leave a Comment » | 2.5D/3D Stacked Integrated Circuits (ICs), DRAM, More than Moore, Packaging (Semiconductor), Probe Card Metrology Tools, Probe Cards, Semiconductor Test, Semiconductor Wafer Test Workshop, Through-Silicon Vias (TSV) | Tagged: DRAM | Permalink
Posted by Ira Feldman
June 28, 2011
Here are the highlights from Session One – “Probe Challenges” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.
Stevan Hunter, ON Semiconductor, “Use of Harsh Wafer Probing to Evaluate Various Bond Pad Structures”:
Recent product needs such as bond [pads] over active circuitry (BOAC), the use of copper (Cu) wire bonding, increased wafer probe touch downs (as many as 6 TDs), and the desire for greater device reliability has driven the need for more robust bond pads to survive wafer probing.
One method for checking for damage to the device from the probing process is via the “Cratering Test”. They etch off the top aluminum (Al) metallization layer of the pad to visually inspect for damage in the underlying titanium-nickel (TiN) barrier metal layer. If there is a problem they can spot a “crater” in the metal. They continue etching to remove the TiN layer to look for additional damage in the layer(s) below.
Read the rest of this entry »
1 Comment | IEEE, MEMS, Packaging (Semiconductor), Probe Cards, Semiconductor Test, Semiconductor Wafer Test Workshop | Tagged: IEEE | Permalink
Posted by Ira Feldman
June 18, 2011
On Sunday evening June 12th, 2011 Jerry Broz, the general conference chair, opened the IEEE Semiconductor Wafer Test Workshop welcoming us to the 21st year with a combined total attendance of over 5,000. He also briefly highlighted the positives in recent market trend data from the Semiconductor Industry Association (SIA) and VLSIresearch.
Dr. William Chen, Senior Technical Advisor, ASE Group, provided the keynote presentation “Backend to the Front Line”:
Dr. Chen started with Read the rest of this entry »
2 Comments | MEMS, Moore's Law, More than Moore, Packaging (Semiconductor), Probe Cards, Semiconductor Test, Semiconductor Wafer Test Workshop, Semiconductors | Tagged: Memory Technology, Semiconductors | Permalink
Posted by Ira Feldman
