Michael Splinter (Applied Materials) - Relative industry cost improvements and volumes.
I hope that my summaries of the first day of SEMI Industry Strategy Symposium (ISS) 2012 in
provided useful insights to the economic roller coaster that is the semiconductor market and its equipment and material supply chain. There have also been several good reports Read the rest of this entry »
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2.5D/3D Stacked Integrated Circuits (ICs), 450 mm wafers, Economics, Moore's Law, SEMI, Semiconductor Capital Equipment (CAPEX), Semiconductors | Tagged: 2.5D/3D Stacked Integrated Circuits (ICs), 450 mm wafers, Economics, Moore's Law, SEMI, Semiconductor Capital Equipment (CAPEX), Semiconductors | 
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Posted by Ira Feldman
After a gloomy first session focused on world economics at SEMI Industry Strategy Symposium (ISS) 2012, Session 2 – Semiconductor Markets was significantly more upbeat.
Stephen G. Newberry (Vice Chairman of the Board, Lam Research Corporation) started off with a way forward in Read the rest of this entry »
Leave a Comment » | 2.5D/3D Stacked Integrated Circuits (ICs), 450 mm wafers, Economics, Moore's Law, SEMI, Semiconductor Capital Equipment (CAPEX), Semiconductors | Tagged: 2.5D/3D Stacked Integrated Circuits (ICs), 450 mm wafers, Economics, Moore's Law, SEMI, Semiconductor Capital Equipment (CAPEX), Semiconductors | Permalink
Posted by Ira Feldman
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Back for the second year (with a minor name change), the Silicon Valley Test Workshop is an unpolished gem. Looking past the rough edges (minor logistical issues), what really shines through is the interaction of the participants. This conference really has Read the rest of this entry »
Leave a Comment » | 2.5D/3D Stacked Integrated Circuits (ICs), Automatic Test Equipment (ATE), Load Boards, Moore's Law, More than Moore, My Presentations, Packaging (Semiconductor), Printed Circuit Boards (PCB), Probe Cards, Semiconductor Test, Test Engineers, Through-Silicon Vias (TSV), ToThePoint | Tagged: 2.5D/3D Stacked Integrated Circuits (ICs), Automatic Test Equipment (ATE), Load Boards, Moore's Law, More than Moore, My Presentations, Packaging (Semicondcutor), Printed Circuit Boards (PCVB), Probe Cards, Semiconductor Test, Test Engineers, Through-Silicon Vias (TSV), ToThePoint | Permalink
Posted by Ira Feldman
On Sunday evening June 12th, 2011 Jerry Broz, the general conference chair, opened the IEEE Semiconductor Wafer Test Workshop welcoming us to the 21st year with a combined total attendance of over 5,000. He also briefly highlighted the positives in recent market trend data from the Semiconductor Industry Association (SIA) and VLSIresearch.
Dr. William Chen, Senior Technical Advisor, ASE Group, provided the keynote presentation “Backend to the Front Line”:
Dr. Chen started with Read the rest of this entry »
2 Comments | MEMS, Moore's Law, More than Moore, Packaging (Semiconductor), Probe Cards, Semiconductor Test, Semiconductor Wafer Test Workshop, Semiconductors | Tagged: Memory Technology, Semiconductors | Permalink
Posted by Ira Feldman
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