April 17, 2012
Speed and Power
If we were focused on just these two parameters, we could be talking about horses, cars, or airplanes. But throw in density, endurance, and price and it is a horse race of different color. Not only does the winning technology have to balance speed and power, it needs to pack more functionality per area at a lower cost than existing solutions. Along with the endurance to last ten or more years.
With annual revenues once exceeding $60 B and now running $45 B due to dropping demand and prices, the global market for semiconductor memory is an exciting race. It is hard to believe that NAND Flash has grown to Read the rest of this entry »
October 17, 2011
Here are the highlights from Session Nine – “Productivity / COO” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 15, 2011.
Doron Avidar, Micron, “Ghosting – Touchdown Reduction Using Alternate Site Sharing“:
Even though memory testers can support very high parallelism, with smaller memories (in terms of capacity and dimensions) there are more die per wafer requiring Read the rest of this entry »
June 17, 2011
Click image to download presentation
As the final presenter at this week’s IEEE Semiconductor Wafer Test Workshop (SWTW), I outlined how critical it is to understand the true cost of a product’s architecture in “Probe Card Cost Drivers from Architecture to Zero Defects“. Without a proper understanding of these costs – especially for fully custom high technology products such as wafer test probe cards – it is impossible to maintain a sufficient gross margin. Gross margin is essential to maintain the health of a company and to fund the research & development required for innovation.
Many companies in the semiconductor test market have entered a period that Steve Newberry identified in his 2008 speech “Semiconductor Industry Trends: The Era of Profitless Prosperity?” that parallels the aluminum industry in the 1970′s. And without the means to fund innovation, companies have no future especially when faced with the double threat of Moore’s Law – increasingly harder technical requirements delivered at lower cost.
Yes, there were a few in the audience who appeared pleased since they are confident that their products are on the right path. There were others who may have been upset based upon their company’s direction. I would argue that a proper diagnosis – regardless of how disturbing – is essential to drive the proper cure.
There is plenty of opportunity in the test market and reasons for optimism. The key to long term prosperity is to really understand the fundamentals of the business and not be blinded by the technology.
I thank those who stayed for the entire conference and welcome your thoughts below. And I will be posting more about the conference (including my summaries) in the next few weeks.
March 24, 2011
…or Memory Magic via More Than Moore
Toshiba 16 Die Stack (64 GB NAND Flash)
No this isn’t a soliloquy to an Apple iPad that is no longer, but a brief tour of the incredible memory, packaging, and system technology that can be found under the hoods of the original iPad and the iPad 2 along with some of the manufacturing and test implications. These devices clearly demonstrate the new paradigm of “More Than Moore“ where scaling of systems and packaging will propel the next wave of growth in electronics beyond the traditional doubling of performance every two years predicted by Moore’s Law. For many in semiconductor packaging and test engineering communities the issues related to More than Moore have been an academic discussion up to now, but clearly the success of the iPad product line shows the current reality for advanced devices and where the future is headed. Apple and their suppliers took huge risks in developing these new technologies in exchange for substantial returns.
As I recently noted in “Memory Alphabet Soup“, the most pressing question about memory most consumers currently have is “which iPad 2?” – 16 GB, 32 GB, or 64 GB? If Mr. Jobs believed in Read the rest of this entry »
March 21, 2011
iSuppli Flash Market Forecast (Jan 2011)
There are so many different types of memory technologies that there is an alphabet soup of acronyms. Ever wonder why we have many different memory technologies some long forgotten with more on the horizon? I refreshed my own memory after last week’s IEEE Nano Technology Council presentation on conductive bridge random access memory (CBRAM).
The simple answer is Read the rest of this entry »
June 7, 2010
Here are the highlights from Session Two – High Temperature Probing of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW)
Keith Breinlinger, FormFactor, “Addressing the Operating Challenges of Full Wafer Contactors”:
Keith started by providing a real good analogy of the challenge of wafer probing in terms of contacting the edge of each sheet of papers in a sixteen high foot stack. He used the new full wafer probe cards SmartMatrix (DRAM) and the TouchMatrix (NAND FLASH) as the basis of his presentation.
Read the rest of this entry »
June 7, 2010
Here are the highlights from Session One – New Contact Technologies of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW)
Jay Kim, Western Specialty Technologies, LLC, “New Probe Card Architecture – Ceramic without MLC”:
He showed how Fine Instrument Co., Ltd. (Korea) built a new probe card architecture which eliminates using multi-layer ceramics (MLCs) to avoid the cost and lead times issues.
Read the rest of this entry »
May 21, 2010
Here are the highlights from Session 6 – Nano-Electronics from day two of the IEEE San Francisco Bay Area Nanotechnology Council 6th Annual Symposium“Nanotechnology: State of the Art & Applications”
Note: I will post the the link for the slides once it becomes available.
Vijendra Sahi, VP Corporate Development and GM of the QD Soleil division, Nanosys, Inc.
“From Concept to Creation: The Journey from R&D to Everyday Products.”