March 14, 2013
Sunset over Phoenix, Arizona during BiTS Workshop
As the Burn-in & Test Strategies (BiTS) Workshop 2013 fades into the sunset (queue the music), here is a round-up of the highlights. There were gun fights in the corral as well as technical questions for the presenters. The saloon girls and gunfighters took an edge off of the “geek” factor. This year over three hundred fifty people come to the “Circle BiTS Ranch” (aka the Hilton in Mesa, Arizona) for the premier conference focused on what is new and next for semiconductor test tooling and strategy. Oh, did I mention that the theme this year was Western?
This was the 14th annual BiTS Workshop, which has achieved the perfect conference trifecta of Read the rest of this entry »
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BiTS Workshop, Cost of Test, DRAM, Interconnectology, Load Boards, Memory Technology, Moore's Law, More than Moore, My Presentations, Packaging (Semiconductor), Printed Circuit Boards (PCB), Probe Cards, Semiconductor Capital Equipment (CAPEX), Semiconductor Test, Semiconductors, Spring Pins, Test Engineers | Tagged: BiTS Workshop, Cost of Test, DRAM, Interconnectology, Load Boards, Memory Technology, Moore's Law, More than Moore, My Presentations, Packaging (Semicondcutor), Printed Circuit Boards (PCB), Probe Cards, Semiconductor Capital Equipment (CAPEX), Semiconductor Test, Semiconductors, Spring Pins, Test Engineers | 
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Posted by Ira Feldman
June 28, 2012
Click image to download presentation
Here are the highlights from Session Four “New Contactor Technologies and RF PCB Design” of the 22nd annual IEEE
Semiconductor Wafer Test Workshop (SWTW) from Monday June 11, 2012.
A last minute change to balance the schedule moved my paper “The Road to 450 mm Semiconductor Wafers” from the previous session:
Many believe that Gordon Moore in his famous 1965 paper “The Experts Look Ahead: Cramming More Components onto Integrated Circuits” that has become know as Moore’s Law, said that the number of transistors on a device would double every year (later revised to every two years). He did not say quite that. What he said was Read the rest of this entry »
Leave a Comment » | 450 mm wafers, Feldman Engineering, IEEE, Load Boards, Moore's Law, My Presentations, Photolithography, Printed Circuit Boards (PCB), Probe Cards, SEMI, Semiconductor Capital Equipment (CAPEX), Semiconductor Test, Semiconductor Wafer Test Workshop, Semiconductors, Simulation | Tagged: 450 mm wafers, Feldman Engineering, IEEE, Load Boards, Moore's Law, My Presentations, Photolithography, Printed Circuit Boards (PCB), Probe Cards, SEMI, Semiconductor Capital Equipment (CAPEX), Semiconductor Test, Semiconductor Wafer Test Workshop, Semiconductors, simulation | Permalink
Posted by Ira Feldman
March 15, 2012
Tim Cook introducing Apple's latest iPad
The “Post Personal Computer” (Post PC) era became the hot topic when Tim Cook introduced the latest iPad last week. Yes, calling it a “revolution” is definitely hype that is part of Apple‘s Post PC marketing campaign. Hype aside, it is clear that there has been a marked shift in digital hardware for the consumption of content and communication. The PC – be it a Windows, Mac, or Linux based system – is no longer “the device”. It is now one of many devices including portable music players (dominated by iPods), smart phones (lead by iPhones and Android based systems), and tablets (dominated by iPads). The shift is large and the impact is huge. To understand how big, watch the first three minutes of Mr. Cook’s presentation. Then you will understand why Apple had the largest market capitalization of any US company in February – the numbers are staggering.
Even though many were surprised to learn that we are now “Post PC”, some of us who have been developing strategies for the electronic supply chain have Read the rest of this entry »
Leave a Comment » | 2.5D/3D Stacked Integrated Circuits (ICs), Apple, Consumer Electronics Society, Load Boards, Market Analysis, MEMS, More than Moore, Packaging (Semiconductor), Post PC Era, Printed Circuit Boards (PCB), Probe Cards, Semiconductors | Tagged: 2.5D/3D Stacked Integrated Circuits (ICs), Apple, Consumer Electronics Society, Load Boards, Market Analysis, MEMS, More than Moore, Packaging (Semicondcutor), Post PC Era, Printed Circuit Boards (PCV), Probe Cards, Semiconductors | Permalink
Posted by Ira Feldman
November 28, 2011
Click image to download presentation
Back for the second year (with a minor name change), the Silicon Valley Test Workshop is an unpolished gem. Looking past the rough edges (minor logistical issues), what really shines through is the interaction of the participants. This conference really has Read the rest of this entry »
Leave a Comment » | 2.5D/3D Stacked Integrated Circuits (ICs), Automatic Test Equipment (ATE), Load Boards, Moore's Law, More than Moore, My Presentations, Packaging (Semiconductor), Printed Circuit Boards (PCB), Probe Cards, Semiconductor Test, Test Engineers, Through-Silicon Vias (TSV), ToThePoint | Tagged: 2.5D/3D Stacked Integrated Circuits (ICs), Automatic Test Equipment (ATE), Load Boards, Moore's Law, More than Moore, My Presentations, Packaging (Semicondcutor), Printed Circuit Boards (PCV), Probe Cards, Semiconductor Test, Test Engineers, Through-Silicon Vias (TSV), ToThePoint | Permalink
Posted by Ira Feldman
June 28, 2010
Here are the highlights from Session Seven – Probe Potpourri of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 8th.
Boyd Daniels, Texas Instruments, “Very Low Cost Probe Cards – A Two Piece Approach”:
For their “catalog” parts – medium complexity, low volume, and medium number of devices – historically it has been cheaper to blind package (i.e. skip wafer test prior to packaging) and take the yield loss at package test. The main issue is the high initial cost and maintenance of probe cards is too high relative to the volume of parts to be tested.
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Leave a Comment » | Automatic Test Equipment (ATE), Load Boards, Printed Circuit Boards (PCB), Probe Card Metrology Tools, Probe Cards, Semiconductor Test, Semiconductor Wafer Test Workshop | Permalink
Posted by Ira Feldman
June 27, 2010
Here are the highlights from Session Five – Signal Integrity of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 8th.
Gert Hohenwarter, GateWave Northern, Inc., “Hidden Performance Limiters in the Signal Path”:
For high frequency signals, designers typically pay attention to avoiding coupling to adjacent signal lines to prevent cross talk. However, they need to look at many other areas of the design including coupling to power or sense lines, signal impedance mismatch, resonances, and the power distribution/delivery system (PDS). Coupling and mismatch may lead to resonances which reduce the operating speed or reduce the switching margin. These areas may also increase crosstalk increasing noise levels and also reducing switching margin. In addition, problems in the PDS may also reduce operating speed or switching margin.
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Leave a Comment » | High Volume Manufacturing (HVM), IEEE, Load Boards, Printed Circuit Boards (PCB), Probe Cards, Semiconductor Test, Semiconductor Wafer Test Workshop | Tagged: IEEE | Permalink
Posted by Ira Feldman
June 8, 2010
Here are the highlights from Session Four – Standards and Methods of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW).
Mark McLaren, Integrated Technology Corporation, “Metrology Solutions for Very Large Probe Cards”:
Over the past few years as the number of memory devices to be tested in parallel has increased so has the size of probe cards to support this multisite testing. A few years ago memory probe cards grew to 440 mm diameter and recently they increased to 480 mm diameter. Now a similar growth in size has been seen for non-memory applications. Even though the parallelism (number of devices to be tested at once) has increased (but not on the scale of memory parallelism), the size increases have been the result of pushing more testing from package test to wafer test. These additional tests have required more local test resources (circuitry close to the device being tested) which require more real estate on probe cards.
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1 Comment | Automatic Test Equipment (ATE), Load Boards, Printed Circuit Boards (PCB), Probe Cards, Semiconductor Test, Semiconductor Wafer Test Workshop | Permalink
Posted by Ira Feldman
May 17, 2010
… and how it impacts your bottom line!
A poorly implemented semiconductor test cell may pass integrated circuit (IC) parts that are either defective or have marginal performance. They can cause the electronic devices in which they will be assembled to either malfunction or completely fail. However, two other conditions require evaluation. Having false negative test “escapes” is expensive in terms of final product test failures, warranty costs, customer dissatisfaction, etc. In turn, the false positive test escapes needs to be balanced against the cost of false negative failures where otherwise good parts fail the tests and are discarded. Test engineers, product managers, quality engineers, and operational managers needs to make either implicit or explicit decisions as to the proper balance in adjusting the test limits. The goal is to cost effectively approach “zero defects” without “throwing out the baby with the bath water”.
A test process generally categorizes the item or device being tested as “pass” or “fail”. Sometimes passing devices are graded (typically by speed or other desired quality) and failing devices are often grouped by failure mode. “Coverage” is how well a particular test process measures the functionality and specifications of a given device. If every feature and specification is tested then it is said to have 100% test coverage. However, exhaustive testing is usually expensive due to long test times which translates in to operational costs including the depreciation of the test system and greater test setup complexity (equipment and development cost). Sometimes complete coverage is not possible or practical so there needs to be a trade-off between coverage and cost.
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Leave a Comment » | Automatic Test Equipment (ATE), Cost of Test, Full Wafer / 1 Touch Down Test, High Volume Manufacturing (HVM), Load Boards, Manufacturing, Probe Cards, Quality, Semiconductor Test, Test Engineers, Yield Improvement | Permalink
Posted by Ira Feldman
