March 14, 2013
Sunset over Phoenix, Arizona during BiTS Workshop
As the Burn-in & Test Strategies (BiTS) Workshop 2013 fades into the sunset (queue the music), here is a round-up of the highlights. There were gun fights in the corral as well as technical questions for the presenters. The saloon girls and gunfighters took an edge off of the “geek” factor. This year over three hundred fifty people come to the “Circle BiTS Ranch” (aka the Hilton in Mesa, Arizona) for the premier conference focused on what is new and next for semiconductor test tooling and strategy. Oh, did I mention that the theme this year was Western?
This was the 14th annual BiTS Workshop, which has achieved the perfect conference trifecta of Read the rest of this entry »
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BiTS Workshop, Cost of Test, DRAM, Interconnectology, Load Boards, Memory Technology, Moore's Law, More than Moore, My Presentations, Packaging (Semiconductor), Printed Circuit Boards (PCB), Probe Cards, Semiconductor Capital Equipment (CAPEX), Semiconductor Test, Semiconductors, Spring Pins, Test Engineers | Tagged: BiTS Workshop, Cost of Test, DRAM, Interconnectology, Load Boards, Memory Technology, Moore's Law, More than Moore, My Presentations, Packaging (Semicondcutor), Printed Circuit Boards (PCB), Probe Cards, Semiconductor Capital Equipment (CAPEX), Semiconductor Test, Semiconductors, Spring Pins, Test Engineers | 
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Posted by Ira Feldman
June 26, 2012
Here are the highlights from Session Three “Probe Potpourri” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 11, 2012.
Larry Levy (FormFactor, Inc.), “Is Parametric Testing About To Enter a Period of Growth and Innovation?”:
Upwards of one thousand facilities perform parametric wafer testing (based on 2009 market data) with over a third of these using obsolete test equipment. There have been no really new testers in several years – Agilent still has their 40xx series and Keithley has their S530 tester. And several companies have exited the market and some companies (including Keithley) are no longer supporting older models of testers. Since parametric testing remains an essential process, this has forced a high number of these facilities to use obsolete equipment or find other approaches. A few companies are going as far as using an Advantest 93000, a significantly more expensive and highly sophisticated digital tester, for parametric test. [Updated to clarify Keithley's status.]
Parametric testing can be divided into three categories: in-line, end of line (EOL), and quality and reliability. In-line testing is Read the rest of this entry »
Leave a Comment » | 450 mm wafers, Cost of Test, IEEE, MEMS, Semiconductor Capital Equipment (CAPEX), Semiconductor Test, Semiconductor Wafer Test Workshop, Test Engineers | Tagged: 450 mm wafers, Cost of Test, IEEE, Semiconductor Capital Equipment (CAPEX), Semiconductor Test, Semiconductor Wafer Test Workshop, Test Engineers | Permalink
Posted by Ira Feldman
June 19, 2012
This year’s IEEE Semiconductor Wafer Test Workshop started on Sunday June 10th with a pleasant surprise. Due to a welcomed but unexpected wave of seventy walk-in registrations, there was insufficient seating at the opening dinner. Thankfully the hotel staff quickly adjusted to accommodate these additional guests. Attendance and interest in this year’s workshop was clearly up.
Jerry Broz, general conference chair, welcomed everyone with a brief overview and presented prizes for the first annual golf tournament. We then quickly proceeded with business as Matt Nowak (Senior Director, Advanced Technology, Qualcomm CDMA Technologies) provided the keynote “Emerging High Density 3D Through Silicon Stacking (TSS) – What’s Next?” Mr. Nowak discussed the increased amount of hype within the 3D semiconductor packaging market in the last year with everyone announcing something. And Thru Silicon Vias (TSVs) technology has already been in high volume production for image sensors for several years now but at a significantly lower density than for 3D packaging.
Why the great interest recently in 3D packaging using TSVs today? Three simple reasons: Read the rest of this entry »
Leave a Comment » | 2.5D/3D Stacked Integrated Circuits (ICs), CMOS Imagers, Cost of Test, High Volume Manufacturing (HVM), IEEE, Mobile Devices, Moore's Law, Packaging (Semiconductor), Semiconductor Test, Semiconductor Wafer Test Workshop, Through-Silicon Vias (TSV) | Tagged: 2.5D/3D Stacked Integrated Circuits (ICs), CMOS Imagers, Cost of Test, High Volume Manufacturing (HVM), IEEE, Mobile Devices, Moore's Law, Packaging (Semicondcutor), Semiconductor Test, Semiconductor Wafer Test Workshop, Through-Silicon Vias (TSV) | Permalink
Posted by Ira Feldman
August 10, 2011
Here are the highlights from Session Five – “Spring Pin Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 14, 2011.
Brandon Mair, Texas Instruments, “WSP-Wafer Socket Probe for Flip Chip Applications“:
Wafer socket probe (WSP) technology has demonstrated better physical and electrical performance and lower cost of ownership (COO) than traditional vertical probe cards for testing wafer level chip scale packages (WLCSP) at 0.4 mm (400 µm) pitch. These WSP probe heads are typically built Read the rest of this entry »
2 Comments | Cost of Test, IEEE, Probe Cards, Semiconductor Capital Equipment (CAPEX), Semiconductor Test, Semiconductor Wafer Test Workshop | Tagged: IEEE | Permalink
Posted by Ira Feldman
June 17, 2011
Click image to download presentation
As the final presenter at this week’s IEEE Semiconductor Wafer Test Workshop (SWTW), I outlined how critical it is to understand the true cost of a product’s architecture in “Probe Card Cost Drivers from Architecture to Zero Defects“. Without a proper understanding of these costs – especially for fully custom high technology products such as wafer test probe cards – it is impossible to maintain a sufficient gross margin. Gross margin is essential to maintain the health of a company and to fund the research & development required for innovation.
Many companies in the semiconductor test market have entered a period that Steve Newberry identified in his 2008 speech “Semiconductor Industry Trends: The Era of Profitless Prosperity?” that parallels the aluminum industry in the 1970′s. And without the means to fund innovation, companies have no future especially when faced with the double threat of Moore’s Law – increasingly harder technical requirements delivered at lower cost.
Yes, there were a few in the audience who appeared pleased since they are confident that their products are on the right path. There were others who may have been upset based upon their company’s direction. I would argue that a proper diagnosis – regardless of how disturbing – is essential to drive the proper cure.
There is plenty of opportunity in the test market and reasons for optimism. The key to long term prosperity is to really understand the fundamentals of the business and not be blinded by the technology.
I thank those who stayed for the entire conference and welcome your thoughts below. And I will be posting more about the conference (including my summaries) in the next few weeks.
2 Comments | Automatic Test Equipment (ATE), Cost of Test, DRAM, FLASH Memory, Full Wafer / 1 Touch Down Test, High Volume Manufacturing (HVM), IEEE, Market Analysis, Multi Layer Ceramics (MLC), My Presentations, Photolithography, Printed Circuit Boards (PCB), Probe Card Metrology Tools, Probe Cards, Product Management, SEMI, Semiconductor Capital Equipment (CAPEX), Semiconductor Test, Semiconductor Wafer Test Workshop, Semiconductors, Space Transformers, Test Engineers | Tagged: DRAM, FLASH Memory, IEEE, SEMI, Semiconductors | Permalink
Posted by Ira Feldman
January 28, 2011
What does your model say?
Even though this sounds like the start of a Carnac the Magnificent comedy act, these are some of the answers from my Probe Card Market model. I keep my model current so I know both industry and company specific performance as well as to make predictions. You don’t have a model? Are you reacting instead of predicting?
So here are the “questions” being answered:
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Leave a Comment » | Cost of Test, Market Analysis, Probe Cards, ToThePoint | Permalink
Posted by Ira Feldman
June 8, 2010
Here are the highlights from Session Three – Improving Cost of Ownership of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW)
Rey Rincon, Freescale & Jeff Greenberg, Rudolph Technologies, “Optimizing Test Cell Performance Using Probing Process Analysis and Predictive Scrub”:
Rey summarized efforts at Freescale to improve test cell performance with multi-tier cantilever probe cards by investigating prober performance, probe card performance and probe card analyzer correlation to the test cell.
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Leave a Comment » | Cost of Test, High Volume Manufacturing (HVM), Probe Cards, Semiconductor Test, Semiconductor Wafer Test Workshop | Permalink
Posted by Ira Feldman
June 7, 2010
Here are the highlights from Session Two – High Temperature Probing of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW)
Keith Breinlinger, FormFactor, “Addressing the Operating Challenges of Full Wafer Contactors”:
Keith started by providing a real good analogy of the challenge of wafer probing in terms of contacting the edge of each sheet of papers in a sixteen high foot stack. He used the new full wafer probe cards SmartMatrix (DRAM) and the TouchMatrix (NAND FLASH) as the basis of his presentation.
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Leave a Comment » | Automatic Test Equipment (ATE), Cost of Test, FLASH Memory, Full Wafer / 1 Touch Down Test, Semiconductor Test, Semiconductor Wafer Test Workshop | Tagged: FLASH Memory | Permalink
Posted by Ira Feldman
May 17, 2010
… and how it impacts your bottom line!
A poorly implemented semiconductor test cell may pass integrated circuit (IC) parts that are either defective or have marginal performance. They can cause the electronic devices in which they will be assembled to either malfunction or completely fail. However, two other conditions require evaluation. Having false negative test “escapes” is expensive in terms of final product test failures, warranty costs, customer dissatisfaction, etc. In turn, the false positive test escapes needs to be balanced against the cost of false negative failures where otherwise good parts fail the tests and are discarded. Test engineers, product managers, quality engineers, and operational managers needs to make either implicit or explicit decisions as to the proper balance in adjusting the test limits. The goal is to cost effectively approach “zero defects” without “throwing out the baby with the bath water”.
A test process generally categorizes the item or device being tested as “pass” or “fail”. Sometimes passing devices are graded (typically by speed or other desired quality) and failing devices are often grouped by failure mode. “Coverage” is how well a particular test process measures the functionality and specifications of a given device. If every feature and specification is tested then it is said to have 100% test coverage. However, exhaustive testing is usually expensive due to long test times which translates in to operational costs including the depreciation of the test system and greater test setup complexity (equipment and development cost). Sometimes complete coverage is not possible or practical so there needs to be a trade-off between coverage and cost.
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Leave a Comment » | Automatic Test Equipment (ATE), Cost of Test, Full Wafer / 1 Touch Down Test, High Volume Manufacturing (HVM), Load Boards, Manufacturing, Probe Cards, Quality, Semiconductor Test, Test Engineers, Yield Improvement | Permalink
Posted by Ira Feldman
