January 22, 2013
Intel shows first fully patterned 450 mm semiconductor wafer at SEMI ISS 2013
Attending the SEMI Industry Strategy Symposium (ISS) is like drinking from a fire hose with the additional risk of whiplash. Don’t get me wrong, it is an exquisite fire hose but sometimes the data presented can be overwhelming at this conference of semiconductor supply chain executives. The majority of the attendees and presenters are executives from the SEMI member companies that develop the equipment, materials, processes, and technology used to build, test, and package semiconductors. And the executives present from the semiconductor manufacturers are typically the “end customers”.
The greatest value of SEMI ISS, beyond the networking, is the strategic overview of the entire semiconductor ecosystem. What are the market drivers, the technology needed, and the roadmap status of this industry? It is true that we all know where we need to head courtesy of Moore’s Law and the International Technology Roadmap for Semiconductors which attempts to keep us on that trajectory. The pressure of consumers needing wanting greater functionality at lower costs is relentless. Much of the technological detail of this ecosystem is addressed in a myriad of other forums throughout the year. ISS ties these technical requirements, development needs, and business needs back to the strategic direction and desires of the global marketplace.
The whiplash comes from Read the rest of this entry »
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2.5D/3D Stacked Integrated Circuits (ICs), 450 mm wafers, Automatic Test Equipment (ATE), Fabs, Healthcare, High Volume Manufacturing (HVM), International Technology Roadmap for Semiconductors (ITRS), Management, Market Analysis, Moore's Law, SEMI, Semiconductor Capital Equipment (CAPEX), Semiconductor Test, Semiconductors | Tagged: 2.5D/3D Stacked Integrated Circuits (ICs), 450 mm wafers, Automatic Test Equipment (ATE), Fabs, Healthcare, High Volume Manufacturing (HVM), International Technology Roadmap for Semiconductors (ITRS), Management, Market Analysis, Moore's Law, SEMI, Semiconductor Capital Equipment (CAPEX), Semiconductor Test, Semiconductors | 
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Posted by Ira Feldman
July 2, 2012
Here are the highlights from Session Five “New Probe Card and Contact Technologies” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 12, 2012.
Tsutomu Shoji (Japan Electronics Materials Corp. ‐ Japan) and Takashi Naito (Advantest ‐ Japan), “Full Wafer Contact Breakthrough with Ultra‐High Pin Count”:
Awarded Best Overall Presentation
As the number of probes on probe cards increase due to greater parallelism, driven by the desire for one touchdown testing and the future transition to 450 mm wafers, the total force required to probe a wafer increases if there is no reduction in the force per probe. This wafer prober chuck needs to apply the required force by pushing the wafer against the probe card typically held in place by the structure of the prober. With 200K probes on a 450 mm wafer each requiring 5 gF this is approximately equal to 1 ton (2205 lbF) of applied force. To reduce these force requirements wafer chuck and prober structure, Advantest and JEM have Read the rest of this entry »
Leave a Comment » | IEEE, Semiconductor Test, Probe Cards, Automatic Test Equipment (ATE), Photolithography, Semiconductor Capital Equipment (CAPEX), Printed Circuit Boards (PCB), Semiconductor Wafer Test Workshop, MEMS, 450 mm wafers, Microfabrication, LIGA | Tagged: IEEE, 450 mm wafers, MEMS, Probe Cards, Semiconductor Capital Equipment (CAPEX), Automatic Test Equipment (ATE), Semiconductor Test, Semiconductor Wafer Test Workshop, Photolithography, Printed Circuit Boards (PCB), Microfabrication, LIGA | Permalink
Posted by Ira Feldman
June 21, 2012
Here are the highlights from the Welcome and Session One “Process Improvements for HVM” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 11, 2012.
Jerry Broz (SWTW general conference chair) started with several sets of numbers: SWTW attendance (up), semiconductor revenue and wafer statistics (problems). and probe card market (up). The problem with semiconductor statistics are Read the rest of this entry »
Leave a Comment » | IEEE, Semiconductor Test, Probe Cards, Automatic Test Equipment (ATE), High Volume Manufacturing (HVM), Full Wafer / 1 Touch Down Test, Semiconductor Wafer Test Workshop, Market Analysis | Tagged: IEEE, High Volume Manufacturing (HVM), Market Analysis, Probe Cards, Automatic Test Equipment (ATE), Semiconductor Test, Semiconductor Wafer Test Workshop, Full Wafer / 1 Touch Down Test | Permalink
Posted by Ira Feldman
November 28, 2011
Click image to download presentation
Back for the second year (with a minor name change), the Silicon Valley Test Workshop is an unpolished gem. Looking past the rough edges (minor logistical issues), what really shines through is the interaction of the participants. This conference really has Read the rest of this entry »
Leave a Comment » | Semiconductor Test, Probe Cards, Load Boards, Automatic Test Equipment (ATE), Test Engineers, Printed Circuit Boards (PCB), More than Moore, ToThePoint, Packaging (Semiconductor), Moore's Law, Through-Silicon Vias (TSV), 2.5D/3D Stacked Integrated Circuits (ICs), My Presentations | Tagged: 2.5D/3D Stacked Integrated Circuits (ICs), Load Boards, More than Moore, Packaging (Semicondcutor), Printed Circuit Boards (PCV), Probe Cards, Moore's Law, Automatic Test Equipment (ATE), My Presentations, Semiconductor Test, Test Engineers, Through-Silicon Vias (TSV), ToThePoint | Permalink
Posted by Ira Feldman
June 17, 2011
Click image to download presentation
As the final presenter at this week’s IEEE Semiconductor Wafer Test Workshop (SWTW), I outlined how critical it is to understand the true cost of a product’s architecture in “Probe Card Cost Drivers from Architecture to Zero Defects“. Without a proper understanding of these costs – especially for fully custom high technology products such as wafer test probe cards – it is impossible to maintain a sufficient gross margin. Gross margin is essential to maintain the health of a company and to fund the research & development required for innovation.
Many companies in the semiconductor test market have entered a period that Steve Newberry identified in his 2008 speech “Semiconductor Industry Trends: The Era of Profitless Prosperity?” that parallels the aluminum industry in the 1970′s. And without the means to fund innovation, companies have no future especially when faced with the double threat of Moore’s Law – increasingly harder technical requirements delivered at lower cost.
Yes, there were a few in the audience who appeared pleased since they are confident that their products are on the right path. There were others who may have been upset based upon their company’s direction. I would argue that a proper diagnosis – regardless of how disturbing – is essential to drive the proper cure.
There is plenty of opportunity in the test market and reasons for optimism. The key to long term prosperity is to really understand the fundamentals of the business and not be blinded by the technology.
I thank those who stayed for the entire conference and welcome your thoughts below. And I will be posting more about the conference (including my summaries) in the next few weeks.
2 Comments | IEEE, Semiconductor Test, Probe Cards, Automatic Test Equipment (ATE), Test Engineers, Cost of Test, High Volume Manufacturing (HVM), Full Wafer / 1 Touch Down Test, Photolithography, Semiconductor Capital Equipment (CAPEX), FLASH Memory, Printed Circuit Boards (PCB), Semiconductor Wafer Test Workshop, Probe Card Metrology Tools, Space Transformers, Multi Layer Ceramics (MLC), Product Management, SEMI, Market Analysis, DRAM, Semiconductors, My Presentations | Tagged: IEEE, DRAM, Semiconductors, FLASH Memory, SEMI | Permalink
Posted by Ira Feldman
November 16, 2010
Starting off something new is often challenging and difficult with many unknowns. Kudos to Nick Langston for creating the Silicon Valley Test Conference that was held last week. (November 8 & 9, 2010) It was the first test conference to actually take place in Silicon Valley. And yes there were some minor “bugs” like registration delays and a no-show by the audio visual contractor that should be solved in next year’s Rev 2.0. Even with a few rough edges, the quality of the presentations and the exhibitors shined through to make this a success.
The conference opened with an excellent keynote address by well-known industry expert Read the rest of this entry »
2 Comments | Automatic Test Equipment (ATE), My Presentations, Semiconductor Test, Semiconductor Wafer Test Workshop, Test Engineers, ToThePoint | Permalink
Posted by Ira Feldman
June 29, 2010
Here are the highlights from Session Eight – Area Array Probing of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 9th.
Senthil Theppakuttai, SV Probe, “Probing Assessment on Fine Pitch Copper Pillar Solder Bumps”:
Flip chips devices are shrinking from 150 µm to 35 µm pitch interconnect. At 150 µm pitch solder balls formed by deposition or electroplating, and stud bumping are typically found. However at tighter pitches down to 35 µm, copper (Cu) pillars with solder caps are the preferred termination. The copper pillars solve electro-migration issues and mechanical/thermal (CTE) mismatch found with solder balls and stud bumping.
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1 Comment | Semiconductor Test, Automatic Test Equipment (ATE), Full Wafer / 1 Touch Down Test, Simulation, Printed Circuit Boards (PCB), Semiconductor Wafer Test Workshop, Space Transformers, Multi Layer Ceramics (MLC) | Permalink
Posted by Ira Feldman
June 28, 2010
Here are the highlights from Session Seven – Probe Potpourri of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 8th.
Boyd Daniels, Texas Instruments, “Very Low Cost Probe Cards – A Two Piece Approach”:
For their “catalog” parts – medium complexity, low volume, and medium number of devices – historically it has been cheaper to blind package (i.e. skip wafer test prior to packaging) and take the yield loss at package test. The main issue is the high initial cost and maintenance of probe cards is too high relative to the volume of parts to be tested.
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Leave a Comment » | Semiconductor Test, Probe Cards, Load Boards, Automatic Test Equipment (ATE), Printed Circuit Boards (PCB), Semiconductor Wafer Test Workshop, Probe Card Metrology Tools | Permalink
Posted by Ira Feldman
June 27, 2010
Here are the highlights from Session Five – Signal Integrity of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 8th.
Jay Thomas, Grund Technical Solutions, LLC., “Probe Cards with Modular Integrated Switching Matrices”:
For the last 30 years, most scribeline parametric testing has been approximately 85% Current-Voltage (I-V) testing and 15% Capacitance-Voltage (C-V) testing. For these types of tests a 10 MHz bandwidth switch matrix has been sufficient.
However, some of the larger fabs such as HP, IBM, and Intel have started performing pulsed Current-Voltage (PIV) and electrostatic discharge (ESD) testing. These customers started this type of testing about four years ago unknown to Agilent & Keithley (the two largest DC parametric tester suppliers). This PIV and ESD testing requires high frequency switch matrices with 1 GHz bandwidth. [For more about ESD testing please see Jay’s second presentation below in this session.]
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Leave a Comment » | Semiconductor Test, Probe Cards, Automatic Test Equipment (ATE), High Volume Manufacturing (HVM), Semiconductor Wafer Test Workshop | Permalink
Posted by Ira Feldman
June 8, 2010
Here are the highlights from Session Four – Standards and Methods of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW).
Mark McLaren, Integrated Technology Corporation, “Metrology Solutions for Very Large Probe Cards”:
Over the past few years as the number of memory devices to be tested in parallel has increased so has the size of probe cards to support this multisite testing. A few years ago memory probe cards grew to 440 mm diameter and recently they increased to 480 mm diameter. Now a similar growth in size has been seen for non-memory applications. Even though the parallelism (number of devices to be tested at once) has increased (but not on the scale of memory parallelism), the size increases have been the result of pushing more testing from package test to wafer test. These additional tests have required more local test resources (circuitry close to the device being tested) which require more real estate on probe cards.
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1 Comment | Semiconductor Test, Probe Cards, Load Boards, Automatic Test Equipment (ATE), Printed Circuit Boards (PCB), Semiconductor Wafer Test Workshop | Permalink
Posted by Ira Feldman
June 7, 2010
Here are the highlights from Session Two – High Temperature Probing of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW)
Keith Breinlinger, FormFactor, “Addressing the Operating Challenges of Full Wafer Contactors”:
Keith started by providing a real good analogy of the challenge of wafer probing in terms of contacting the edge of each sheet of papers in a sixteen high foot stack. He used the new full wafer probe cards SmartMatrix (DRAM) and the TouchMatrix (NAND FLASH) as the basis of his presentation.
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Leave a Comment » | Automatic Test Equipment (ATE), Cost of Test, FLASH Memory, Full Wafer / 1 Touch Down Test, Semiconductor Test, Semiconductor Wafer Test Workshop | Tagged: FLASH Memory | Permalink
Posted by Ira Feldman
June 6, 2010
The 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW) started this evening. Rumor has it that attendance is over 240 this year which is a vast improvement over last year’s 160 or so attendees. At the peak the conference had almost hit 600. Things started off well with a reception where I had the chance to catch up with many industry friends and colleagues.
After dinner, Jerry Broz the General Chair kicked things off with the “Probe Year in Review”. In summary:
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Leave a Comment » | Automatic Test Equipment (ATE), Clean Tech (Green), IEEE, Probe Cards, Semiconductor Capital Equipment (CAPEX), Semiconductor Test, Semiconductor Wafer Test Workshop, Solar | Tagged: IEEE | Permalink
Posted by Ira Feldman
May 17, 2010
… and how it impacts your bottom line!
A poorly implemented semiconductor test cell may pass integrated circuit (IC) parts that are either defective or have marginal performance. They can cause the electronic devices in which they will be assembled to either malfunction or completely fail. However, two other conditions require evaluation. Having false negative test “escapes” is expensive in terms of final product test failures, warranty costs, customer dissatisfaction, etc. In turn, the false positive test escapes needs to be balanced against the cost of false negative failures where otherwise good parts fail the tests and are discarded. Test engineers, product managers, quality engineers, and operational managers needs to make either implicit or explicit decisions as to the proper balance in adjusting the test limits. The goal is to cost effectively approach “zero defects” without “throwing out the baby with the bath water”.
A test process generally categorizes the item or device being tested as “pass” or “fail”. Sometimes passing devices are graded (typically by speed or other desired quality) and failing devices are often grouped by failure mode. “Coverage” is how well a particular test process measures the functionality and specifications of a given device. If every feature and specification is tested then it is said to have 100% test coverage. However, exhaustive testing is usually expensive due to long test times which translates in to operational costs including the depreciation of the test system and greater test setup complexity (equipment and development cost). Sometimes complete coverage is not possible or practical so there needs to be a trade-off between coverage and cost.
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Leave a Comment » | Manufacturing, Semiconductor Test, Probe Cards, Load Boards, Automatic Test Equipment (ATE), Test Engineers, Cost of Test, Quality, High Volume Manufacturing (HVM), Full Wafer / 1 Touch Down Test, Yield Improvement | Permalink
Posted by Ira Feldman
